5SGXEB6R3F43C4 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Programmable logic devices> Programmable logic> 5SGXEB6R3F43C4

5SGXEB6R3F43C4: Descriptionfpga - field programmable gate array fpga - stratix V GX 2660 labs 600 ios; CategoryProgrammable logic devices Programmable logic; File Size406KB，21 Pages; ManufacturerAltera (Intel)

Download Datasheet Parametric View All

5SGXEB6R3F43C4 Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	5SGXEB6R3F43C4	-	-	View	Buy Now

5SGXEB6R3F43C4 Overview

fpga - field programmable gate array fpga - stratix V GX 2660 labs 600 ios

5SGXEB6R3F43C4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
package instruction	FBGA-1760
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B1760
length	42.5 mm
Configurable number of logic blocks	22540
Number of entries	600
Number of logical units	597000
Output times	600
Number of terminals	1760
Maximum operating temperature	85 °C
Minimum operating temperature
organize	22540 CLBS
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1760,42X42,40
Package shape	SQUARE
Package form	GRID ARRAY
power supply	0.85,1.5,2.5,2.5/3,1.2/3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.4 mm
Maximum supply voltage	0.88 V
Minimum supply voltage	0.82 V
Nominal supply voltage	0.85 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	42.5 mm

Preview

Download Datasheet

View All

2014.04.08

Stratix V Device Overview

Send Feedback

SV51001

Many of the Stratix

V devices and features are enabled in the Quartus

II software version 13.0. The

remaining devices and features will be enabled in future versions of the Quartus II software.

Altera’s 28-nm Stratix V FPGAs include innovations such as an enhanced core architecture, integrated

transceivers up to 28.05 gigabits per second (Gbps), and a unique array of integrated hard intellectual property

(IP) blocks. With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices

optimized for:

• Bandwidth-centric applications and protocols, including PCI Express

(PCIe

) Gen3

• Data-intensive applications for 40G/100G and beyond

• High-performance, high-precision digital signal processing (DSP) applications

Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a different set of

applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low-risk,

low-cost path to HardCopy

V ASICs.

Related Information

•

Stratix V Device Handbook: Known Issues

Lists the planned updates to the

Stratix V Device Handbook

chapters.

•

Upcoming Stratix V Device Features

Stratix V Family Variants

The Stratix V device family contains the GT, GX, GS, and E variants.

Stratix V GT

devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are optimized for applications that

require ultra-high bandwidth and performance in areas such as 40G/100G/400G optical communications

systems and optical test systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and GX

channels, respectively.

Stratix V GX

devices offer up to 66 integrated transceivers with 14.1-Gbps data rate capability. These

transceivers also support backplane and optical interface applications. These devices are optimized for high-

performance, high-bandwidth applications such as 40G/100G optical transport, packet processing, and

traffic management found in wireline, military communications, and network test equipment markets.

Stratix V GS

devices have an abundance of variable precision DSP blocks, supporting up to 3,926 18x18 or

1,963 27x27 multipliers. In addition, Stratix V GS devices offer integrated transceivers with 14.1-Gbps data

rate capability. These transceivers also support backplane and optical interface applications. These devices

and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other

words and logos identified as trademarks or service marks are the property of their respective holders as described at

www.altera.com/common/legal.html.

Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes

no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly

agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published

information and before placing orders for products or services.

ISO

9001:2008

Registered

www.altera.com

101 Innovation Drive, San Jose, CA 95134

Recommended Resources

DZL33-10 leakage protector circuit

The single-phase electric energy meter of the two-phase circuit is connected to the circuit through the current transformer.

KPY series silicon piezoresistive absolute pressure sensor circuit 02

Continuous flow pulse detection circuit

SCR AC voltage regulator

M51242P (TV and audio equipment) 3-function infrared remote control receiving circuit

About MCU hardware anti-interference (transfer): When developing electronic products with processors, how to improve anti-interference ability and electromagnetic compatibility? 1. The following systems should pay special attention to anti-electroma...; boyfly Energy Infrastructure?

Looking for a power indicator light circuit: I want to make a power indicator light circuit, but I find that what I made doesn't work. Conditions: power supply voltage +5V, red LED, NOR gate. Requirements: When the power supply is sufficient, th...; x810421 Embedded System

mcsdk edma3_lld compilation error: I am using mcsdk_1_01_00_02. When I enter the directory edma3_lld_02_11_09_08/examples/edma3_driver/evmOMAPL138 to compile the edma3 example, the following error occurs: root@silent:/opt/ti/edma3_lld_...; 倚楼、听风雨 DSP and ARM Processors

About the write operation of NOR flash: Original post address: http://topic.eeworld.net/u/20080521/16/8dd26e1c-2e9b-4277-877b-5f888125bc35.html?seed=2142211368 Our current system uses Samsung 44b0 platform, an 8M sram, an 8M nor flash, and ...; fjjiin Embedded System

Gaofen asks: How does CPM in the MPC82xx series PPC work?: The CPM module of powerpc integrates many communication protocols. I am not very clear about some of them. For example: a 10M UDP packet comes in from the FCC network port, which cannot be transmitted...; djf876 Embedded System

TI C6000 Software Development Process and Program Optimization Technology: [size=4] The software development process of TI C6000 focuses on the C/C++ program optimization technology of the C6000 series, including optimization process, C/C++ code optimization method, and line...; 灞波儿奔 DSP and ARM Processors

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components