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EH2520ETTS-3.57954MTR

Description
CRYSTAL OSCILLATOR, CLOCK, CMOS OUTPUT
CategoryPassive components    oscillator   
File Size935KB,10 Pages
ManufacturerECLIPTEK
Websitehttp://www.ecliptek.com
Environmental Compliance
Download Datasheet Parametric View All

EH2520ETTS-3.57954MTR Overview

CRYSTAL OSCILLATOR, CLOCK, CMOS OUTPUT

EH2520ETTS-3.57954MTR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid7039749481
Reach Compliance Codecompliant
Other featuresTRI-STATE; ENABLE/DISABLE FUNCTION; TR, 14 INCH
maximum descent time6 ns
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Number of terminals4
Nominal operating frequency3.57954 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
Output load30 pF
physical size7.0mm x 5.0mm x 1.6mm
longest rise time6 ns
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry60/40 %
Terminal surfaceNickel/Gold (Ni/Au)
Ecliptek | EH25 Series Oscillator
http://www.ecliptek.com/oscillators/EH25/
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| 714-433-1200 |
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EH25 Series Oscillator
Quartz Crystal Clock Oscillators XO (SPXO) HCMOS/TTL (CMOS) 5.0Vdc 4 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)
2011/65 +
2015/863
168 SVHC
Revision G 06/08/2012
Electrical Specifications
Nominal Frequency
1.000MHz to 155.520MHz
Some frequencies within this range may not be available.
Frequency Tolerance/Stability
(Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency
Stability over the Operating Temperature Range, Supply Voltage
Change, Output Load Change, First Year Aging at 25°C, Shock, and
Vibration)
±100ppm Maximum
±50ppm Maximum
±25ppm Maximum
±20ppm Maximum
±5ppm/year Maximum
0°C to +70°C
-40°C to +85°C
5.0V
DC
±10%
No Load
50mA Maximum
I
OH
= -16mA
2.4V
DC
Minimum with TTL Load, V
DD
-0.4V
DC
Minimum with HCMOS
Load
I
OL
= +16mA
0.4V
DC
Maximum with TTL Load, 0.5V
DC
Maximum with HCMOS Load
50 ±10(%) Measured at 1.4V
DC
with TTL Load or at 50% of waveform
with HCMOS Load from 1MHz to 70MHz Measured at 50% of waveform
above 70MHz
50 ±5(%) Measured at 50% of waveform
Measured at 0.8V
DC
to 2.0V
DC
with TTL Load; Masured at 20% to 80%
of waveform with HCMOS Load
6nSec Maximum from 1MHz to 70MHz
4nSec Maximum from 70.000001MHz to 155.520MHz
10 TTL Load or 50pF HCMOS Load Maximum from 1MHz to 70MHz
5 TTL Load or 15pF HCMOS Load Maximum from 70.000001MHz to
155.520MHz
CMOS
Tri-State (High Impedance)
+2.2V
DC
Minimum to Enable Output, +0.8V
DC
Maximum to Disable
Output (High Impedance), No Connect to Enable Output
±250pSec Maximum, ±100pSec Typical
±50pSec Maximum, ±30pSec Typical
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (V
OH
)
Output Voltage Logic Low (V
OL
)
Duty Cycle
Rise Time/Fall Time
Load Drive Capability
Output Logic Type
Pin 1 Connection
Tri-State Input Voltage (Vih and Vil)
Absolute Clock Jitter
One Sigma Clock Period Jitter
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