Freescale Semiconductor
Addendum
Document Number: QFN_Addendum
Rev. 0, 07/2014
Addendum for New QFN
Package Migration
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806:
Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
Part Number
MC68HC908JW32
MC9S08AC16
MC9S908AC60
MC9S08AC128
MC9S08AW60
MC9S08GB60A
MC9S08GT16A
MC9S08JM16
MC9S08JM60
MC9S08LL16
MC9S08QE128
MC9S08QE32
MC9S08RG60
MCF51CN128
MC9RS08LA8
MC9S08GT16A
MC9S908QE32
MC9S908QE8
MC9S08JS16
MC9S08QB8
MC9S08QG8
MC9S08SH8
MC9RS08KB12
MC9S08QG8
MC9RS08KB12
MC9S08QG8
MC9RS08KA2
6 DFN
Package Description
48 QFN
Original (gold wire)
Current (copper wire)
package document number package document number
98ARH99048A
98ASA00466D
48 QFN
32 QFN
32 QFN
32 QFN
24 QFN
98ARL10606D
98ARH99035A
98ARE10566D
98ASA00071D
98ARL10608D
98ASA00466D
98ASA00473D
98ASA00473D
98ASA00736D
98ASA00734D
24 QFN
24 QFN
24 QFN
16 QFN
8 DFN
98ARL10605D
98ARE10714D
98ASA00087D
98ARE10614D
98ARL10557D
98ASA00474D
98ASA00474D
98ASA00602D
98ASA00671D
98ASA00672D
98ARL10602D
98ASA00735D
Addendum for New QFN Package Migration, Rev. 0
2
Freescale Semiconductor
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9RS08LA8
Rev. 2, 1/2012
MC9RS08LA8
48 QFN
Case 1975
7 mm
2
TBD
48 LQFP
Case 932
7 mm
2
MC9RS08LA8
Features:
• 8-Bit RS08 Central Processor Unit (CPU)
– Up to 20 MHz CPU at 2.7 V to 5.5 V across temperature
range of –40°C to 85°C
– Subset of HC08 instruction set with added BGND
instruction
• On-Chip Memory
– 8 KB flash read/program/erase over full operating
voltage and temperature
– 256-byte random-access memory (RAM)
– Security circuitry to prevent unauthorized access to flash
contents
• Power-Saving Modes
– Wait and stop
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
39.0625 kHz or 1 MHz to 16 MHz
– Internal clock source (ICS) — Internal clock source
module containing a frequency-locked-loop (FLL)
controlled by internal or external reference; supports bus
frequencies up to 10 MHz
• System Protection
– Watchdog computer operating properly (COP) reset
with option to run from dedicated 1 kHz internal clock
source or bus clock
– Low-voltage detection with reset or interrupt; selectable
trip points
– Illegal opcode detection with reset
– Illegal address detection with reset
– Flash block protection
• Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
• Peripherals
–
LCD
— Up to 8
×
21 or 4
×
25 segments; compatible
with 5 V or 3 V LCD glass displays using on-chip charge
pump; functional in wait, stop modes for very low power
LCD operation; frontplane and backplane pins
multiplexed with GPIO functions; selectable frontplane
and backplane configurations
–
ADC
— 6-channel, 10-bit resolution; 2.5
μs
conversion
time; automatic compare function; 1.7 mV/°C
temperature sensor; internal bandgap reference channel;
operation in stop; fully functional from 2.7 V to 5.5 V.
–
TPM
— One 2-channel 16-bit timer/pulse-width
modulator (TPM) module
–
SCI
— One 2-channel serial communications interface
module with optional 13-bit break; LIN extensions
–
SPI
— One serial peripheral interface module in 8-bit
data length mode with a receive data buffer hardware
match function
–
ACMP
— Analog comparator with option to compare to
internal reference
–
MTIM
— One 8-bit modulo timer
–
KBI
— 8-pin keyboard interrupt module
–
RTI
— One real-time interrupt module with optional
reference clock.
• Input/Output
– 33 GPIOs including 1 output only pin and 1 input only
pin.
– Hysteresis and configurable pullup device on all input
pins; configurable slew rate and drive strength on all
output pins.
• Package Options
– 48-pin QFN
– 48-pin LQFP
This document contains information on a product under development. Freescale reserves
the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2012. All rights reserved.
Table of Contents
1
2
3
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .7
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .8
3.4 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .9
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .14
3.7 External (XOSC) and Internal (ICS) Oscillator
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.8.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 TPM/MTIM Module Timing . . . . . . . . . . . . . . . .
3.9 Analog Comparator (ACMP) Electrical . . . . . . . . . . . .
3.10 Internal Clock Source Characteristics . . . . . . . . . . . . .
3.11 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information and Mechanical Drawings . . . . . . . . . .
17
18
19
19
20
22
22
23
25
26
4
5
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
1
2
Date
10/9/2008
1/30/2012
Initial public released.
Updated the case number of 48-pin QFN to 1975; updated 48-pin QFN case outline drawing.
Description of Changes
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com
Reference Manual
(MC9RS08LA8RM)
Contains extensive product information including modes of operation, memory, resets and
interrupts, register definition, port pins, CPU, and all module information.
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
2
Freescale Semiconductor
MCU Block Diagram
1
V
REFH
V
REFL
V
DDAD
V
SSAD
MCU Block Diagram
6-CH 10-BIT
ANALOG-TO-DIGITAL
CONVERTER(ADC)
4-BIT KEYBORAD
RS08 CORE
INTERRUPT(KBI)
SERIAL PERIPHERAL
INTERFACE (SPI)
ANALOG COMPARATOR
(ACMP)
RS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
WAKEUP
V
PP
RTI
2-CH TIMER/PWM
LVD
MODULE (TPM)
RESET
XTAL
EXTAL
TPMCH0
TPMCH1
TCLK
PTA0/SS/KBIP0/ADP0/LCD27
PTA1/SPSCK/KBIP1/ADP1/LCD26
KBIP[0:7]
SS
SPSCK
MISO
MOSI
ACMP+
ACMP–
ACMPO
The block diagram,
Figure 1,
shows the structure of the MC9RS08LA8 MCU.
ADP[5:0]
PORT A
PTA2/MISO/KBIP2/ADP2/RxD/LCD25
PTA3/MOSI/KBIP3/ADP3/TxD/LCD24
PTA4/KBIP4/ADP4/LCD23
PTA5/KBIP5/ADP5/LCD22
PTA6/KBIP6/ACMP+
PTA7/KBIP7/ACMP–
CPU
BDC
PORT B
PTB0/EXTAL
PTB1/XTAL
PTB2/RESET/V
PP
PTC0/RxD
PORT C
PTC1/TxD
PTC2/TPMCH0
PTC3/TPMCH1
PTC6/ACMPO/BKGD/MS
PTC7/TCLK/LCD28
PTD0/LCD0
PTD1/LCD1
USER FLASH
8192 BYTES
USER RAM
256 BYTES
20 MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
SERIAL COMMUNICATION
INTERFACE (SCI)
TxD
RxD
PORT D
31.25 kHz to 38.4 kHz
1 MHz to 16 MHz
(XOSC)
8-bit Modulo Timer
(MTIM)
TCLK
PTD2/LCD2
PTD3/LCD3
PTD4/LCD4
PTD5/LCD5
PTD6/LCD6
V
DD
V
SS
VOLTAGE REGULATOR
LCD[0:7]
V
LL1
V
LL2
V
LL3
V
CAP1
V
CAP2
LCD28
LIQUID CRYSTAL DISPLAY
DRIVER (LCD)
LCD[16:21]
LCD[22:27]
LCD[8:15]
PTD7/LCD7
PTE0/LCD8
PTE1/LCD9
PORT E
PTE2/LCD10
PTE3/LCD11
PTE4/LCD12
PTE5/LCD13
PTE6/LCD14
PTE7/LCD15
LCD[16:21]
NOTES:
1. PTB2/RESET/V
PP
is an input only pin when used as port pin
2. PTC6/ACMPO/BKGD/MS is an output only pin
Figure 1. MC9RS08LA8 Series Block Diagram
MC9RS08LA8 Series MCU Data Sheet, Rev. 2
Freescale Semiconductor
3
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