MM74HCT240 • MM74HCT244 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
February 1984
Revised May 2005
MM74HCT240 • MM74HCT244
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HCT240 and MM74HCT244 3-STATE buffers
utilize advanced silicon-gate CMOS technology and are
general purpose high speed inverting and non-inverting
buffers. They possess high drive current outputs which
enable high speed operation even when driving large bus
capacitances. These circuits achieve speeds comparable
to low power Schottky devices, while retaining the low
power consumption of CMOS. All three devices are TTL
input compatible and have a fanout of 15 LS-TTL equiva-
lent inputs.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
The MM74HCT240 is an inverting buffer and the
MM74HCT244 is a non-inverting buffer. Each device has
two active low enables (1G and 2G), and each enable inde-
pendently controls 4 buffers.
All inputs are protected from damage due to static dis-
charge by diodes to V
CC
and Ground.
Features
s
TTL input compatible
s
Typical propagation delay: 14 ns
s
3-STATE outputs for connection to system buses
s
Low quiescent current: 80
P
A
s
High output drive current: 6 mA (min)
Ordering Code:
Order Number
MM74HCT240WM
MM74HCT240SJ
MM74HCT240MTC
MM74HCT240N
MM74HCT244WM
MM74HCT244SJ
MM74HCT244MTC
MM74HCT244N
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HCT240
Top View
MM74HCT244
© 2005 Fairchild Semiconductor Corporation
DS005365
www.fairchildsemi.com
MM74HCT240 • MM74HCT244
Absolute Maximum Ratings
(Note 1)
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
Clamp Diode Current (I
IK
, I
OK
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
q
C
600 mW
500 mW
Recommended Operating
Conditions
Min
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
)
Input Rise or Fall Times
(t
r
, t
f
)
500
ns
Note 1:
Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
0.5 to
7.0V
1.5 to V
CC
1.5V
0.5 to V
CC
0.5V
r
20 mA
r
35 mA
r
70 mA
65
q
C to
150
q
C
Max
5.5
V
CC
Units
V
V
4.5
0
40
85
q
C
DC Electrical Characteristics
V
CC
5V
r
10% (unless otherwise specified)
Parameter
Minimum HIGH Level
Input Voltage
V
IL
V
OH
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
IN-EE
|I
OUT
|
|I
OUT
|
|I
OUT
|
V
OL
Maximum LOW Level
Voltage
V
IN
|I
OUT
|
|I
OUT
|
|I
OUT
|
I
IN
I
OZ
Maximum Input
Current
Maximum 3-STATE
Output Leakage
Current
I
CC
Maximum Quiescent
Supply Current
V
IN
V
OUT
G
G
V
IN
I
OUT
V
IN
V
IH
V
IL
V
CC
or GND
0
P
A
2.4V or 0.5V (Note 4)
0.6
1.0
1.3
1.5
mA
4.0
40
160
V
IH
or V
IL
20
P
A
6.0 mA, V
CC
7.2 mA, V
CC
V
IH
or V
IL
20
P
A
6.0 mA, V
CC
7.2 mA, V
CC
V
CC
or GND,
V
CC
or GND
4.5V
5.5V
0
0.2
0.2
0.1
0.26
0.26
0.1
0.33
0.33
0.1
0.4
0.4
V
V
V
4.5V
5.5V
V
CC
4.2
5.2
V
CC
0.1
3.98
4.98
V
CC
0.1
3.84
4.84
V
CC
0.1
3.7
4.7
V
V
V
0.8
0.8
0.8
V
Conditions
T
A
Typ
2.0
25
q
C
T
A
Symbol
V
IH
40 to 85
q
C T
A
55
q
to 125
q
C
Guaranteed Limits
2.0
2.0
Units
V
r
0.05
r
0.25
r
0.5
r
2.5
r
1.0
r
10
P
A
P
A
V
IH
or V
IL
P
A
Note 4:
Measured per input. All other inputs at V
CC
or GND.
3
www.fairchildsemi.com
Real-time operating system RTOS
京公网安备 11010802033920号
EEWORLD
