INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40097B
buffers
3-state hex non-inverting buffer
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
3-state hex non-inverting buffer
DESCRIPTION
The HEF40097B is a hex non-inverting buffer with 3-state
outputs. The 3-state outputs are controlled by two enable
inputs (EO
4
and EO
2
). A HIGH on EO
4
causes four of the
six buffer elements to assume a high impedance or
OFF-state, regardless of the other input conditions and a
HIGH on EO
2
causes the outputs of the remaining two
buffer elements to assume a high impedance or
OFF-state, regardless of the other input conditions.
HEF40097B
buffers
Fig.2 Pinning diagram.
HEF40097BP(N):
HEF40097BD(F):
HEF40097BT(D):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
I
1
to I
6
EO
4
, EO
2
O
1
to O
6
buffer inputs
enable inputs (active LOW)
buffer outputs (active HIGH)
Fig.1 Functional diagram.
FAMILY DATA, I
DD
LIMITS category BUFFERS
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
3-state hex non-inverting buffer
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
I
n
→
O
n
HIGH to LOW
5
10
15
5
LOW to HIGH
Output transition times
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
3-state propagation delays
Output disable times
EO
2
, EO
4
→
O
n
HIGH
5
10
15
5
LOW
Output enable times
EO
2
, EO
4
→
O
n
HIGH
5
10
15
5
LOW
10
15
t
PZL
t
PZH
75
35
30
95
40
30
150
70
60
190
80
65
ns
ns
ns
ns
ns
ns
10
15
t
PLZ
t
PHZ
45
35
30
60
35
25
95
70
60
120
70
55
ns
ns
ns
ns
ns
ns
10
15
t
TLH
t
THL
t
PLH
t
PHL
70
30
25
60
25
20
30
15
10
35
20
15
140
60
50
120
50
40
60
30
20
70
40
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
TYP.
MAX.
HEF40097B
buffers
TYPICAL EXTRAPOLATION
FORMULA
60 ns
+
(0,20 ns/pF) C
L
26 ns
+
(0,08 ns/pF) C
L
22 ns
+
(0,06 ns/pF) C
L
45 ns
+
(0,30 ns/pF) C
L
19 ns
+
(0,13 ns/pF) C
L
16 ns
+
(0,09 ns/pF) C
L
15 ns
+
(0,30 ns/pF) C
L
10 ns
+
(0,11 ns/pF) C
L
7 ns
+
(0,07 ns/pF) C
L
10 ns
+
(0,50 ns/pF) C
L
8 ns
+
(0,24 ns/pF) C
L
6 ns
+
(0,18 ns/pF) C
L
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
5 400 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
25 200 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
96 500 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load cap. (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
4
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