out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain
the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. C
12/01/09
1
IS42S32800D, IS45S32800D
DEVICE OVERVIEW
The 256Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V V
dd
and 3.3V V
ddq
memory systems containing 268,435,456
bits. Internally configured as a quad-bank DRAM with a
synchronous interface. Each 67,108,864-bit bank is orga-
nized as 4,096 rows by 512 columns by 32 bits.
The 256Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 256Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM (FOR 2M
x
32
x
4
BANKS)
CLK
CKE
CS
RAS
CAS
WE
DQM0 - DQM3
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
32
32
4
MODE
REGISTER
12
REFRESH
CONTROLLER
DQ 0-31
SELF
REFRESH
CONTROLLER
A10
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
12
32
DATA OUT
BUFFER
V
DD
/V
DDQ
V
ss
/V
ss
Q
32
REFRESH
COUNTER
4096
4096
4096
4096
ROW DECODER
MULTIPLEXER
12
MEMORY CELL
ARRAY
ROW
ADDRESS
LATCH
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
9
512
(x 32)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
9
2
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. C
12/01/09
IS42S32800D, IS45S32800D
PIN CONFIGURATIONS
86 pin TSOP - Type II for x32
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
DQM0
WE
CAS
RAS
CS
A11
BA0
BA1
A10
A0
A1
A2
DQM2
V
DD
NC
DQ16
V
SS
Q
DQ17
DQ18
V
DD
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
DD
Q
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
DD
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
DD
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
V
dd
Vss
V
ddq
Vss
q
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. C
12/01/09
3
IS42S32800D, IS45S32800D
PIN CONFIGURATION
PACKAGE CODE: B 90 BALL TF-BGA (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
PIN DESCRIPTIONS
A0-A11
A0-A8
BA0, BA1
DQ0 to DQ31
CLK
CKE
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
DQM0-DQM3
V
dd
Vss
V
ddq
Vss
q
NC
Write Enable
x32 Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
DQ26 DQ24
VSS
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC
A2
A10
NC
BA0
CAS
VDD
DQ6
DQ1
DQ16 VSSQ
DQM2 VDD
A0
BA1
CS
A1
A11
RAS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31
VSS DQM3
A4
A7
CLK
DQM1
A5
A8
CKE
NC
NC
A3
A6
NC
A9
NC
VSS
WE
DQM0
DQ7 VSSQ
DQ5 VDDQ
DQ3 VDDQ
VDDQ DQ8
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15
VSS
VDDQ VSSQ DQ4
VDD
DQ0
DQ2
4
Integrated Silicon Solution, Inc.
- www.issi.com
Rev. C
12/01/09
IS42S32800D, IS45S32800D
PIN FUNCTIONS
Symbol
A0-A11
Type
Input Pin
Function (In Detail)
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE command (column address
A0-A8), with A10 defining auto precharge) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ, WRITE
or PRECHARGE command is being applied.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
"Command Truth Table" for details on device commands.
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When CKE
is LOW, the device will be in either power-down mode, clock suspend mode, or self
refresh mode. CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device
are acquired in synchronization with the rising edge of this pin.
The CS input determines whether command input is enabled within the device.
Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when
CS is HIGH.
DQM0 - DQM3 control the four bytes of the I/O buffers (DQ0-DQ31). In read
mode, DQMn control the output buffer. When DQMn is LOW, the corresponding buf-
fer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH imped-
ance state whenDQMn is HIGH. This function corresponds to OE in conventional
DRAMs. In write mode, DQMn control the input buffer. When DQMn is LOW, the
corresponding buffer byte is enabled, and data can be written to the device. When
DQMn is HIGH, input data is masked and cannot be written to the device.
Data on the Data Bus is latched on these pins during Write commands, and buffered after
Read commands.
RAS,
in conjunction with
CAS
and
WE,
forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
WE,
in conjunction with
RAS
and
CAS,
forms the device command. See the "Com-
mand Truth Table" item for details on device commands.
When a USB flash drive is inserted into a Windows system, the system will automatically recognize it. How can I prevent the system from recognizing it? Can I make a driver myself to control this USB f...
[font=normal 宋体, Arial, Helvetica, sans-serif][color=#000000][size=12px] In the read mode of the hardware I2C of MSP430G2253, the slave byte address is sent first, and then it is directly converted to...
I haven't drawn PCB for a long time. Recently, I have a motor board to make. I drew a motor board again using Allegro 16.6. The last time I drew a board was 2 years ago. This time I picked up Alidog a...
[i=s]This post was last edited by littleshrimp on 2021-9-18 12:29[/i]I bought a few night vision cameras on a certain website. This one is the NV3 version, which uses a 4-pin HSD connector and is smal...
I want my MCU to send a series of commands to control the fingerprint module. When I connect the serial port of the MCU to the PC, I can see that the MCU correctly sends a series of commands to the PC...
The core of a machine vision system is image acquisition and processing. All information comes from images, and image quality is crucial to the entire vision system. A good image can improve the st...[Details]
Reflow soldering, a common soldering method in modern electronics manufacturing, primarily melts solder paste and pads to form solder joints. With technological advancements, soldering equipment ha...[Details]
Today's security industry has entered the era of massive networking. Many enterprises, especially financial institutions, have established multi-level video surveillance networking platforms. Lever...[Details]
The automotive industry in 2025 is undergoing a thorough intelligent reshuffle.
Geely wants to make changes in the field of AI cockpits: in the future, there will be no traditional smart...[Details]
Overview
As handheld voice communication devices become more and more popular, they are increasingly used in noisy environments, such as airports, busy roads, crowded bars, etc. In such noisy ...[Details]
Intel®
Xeon®
6
-
core processors now support the new Amazon EC2 R8i and R8i-flex instances on Amazon Web Services (AWS).
These new instances offer superior performance and fast...[Details]
Tools/Materials
Yitong Chuanglian MODBUS to PROFIBUS Gateway YT-PB-03
Siemens s7-300
This article describes how to configure the YT-PB-03 MODBUS to PROFIBUS gat...[Details]
MQTT Ethernet I/O modules primarily collect I/O port information and transmit data over the network. In addition to being a TCP server, Ethernet I/O modules can also function as TCP clients. Furthe...[Details]
The driving mode is not unfamiliar to vehicles. According to the driving mode of the vehicle, there are front-wheel drive, rear-wheel drive and even four-wheel drive. Four-wheel drive is a major se...[Details]
New version helps developers build secure and trustworthy embedded systems
Shanghai, China—August 21, 2025—
QNX, a division of BlackBerry Ltd., today announced the release of QNX...[Details]
The composition of the water heater
The water heater itself is divided into the following parts:
1. Water tank.
This is where the water heater is filled with water and where the wate...[Details]
Silicon Labs (also known as "Silicon Labs"), an innovative leader in low-power wireless connectivity, will showcase its cutting-edge artificial intelligence (AI) and Internet of Things (IoT) solu...[Details]
Let’s first take a look at the development concept of the EVD series.
The EVD control module is specially developed for operation in extreme environments. Components that meet these requiremen...[Details]
Yongxin Technology's BCL603S2H chipset integrates the nRF54L15 system-on-chip for monitoring various sensors and achieving seamless wireless connectivity.
Oslo, Norway – August 19, 2...[Details]
STM8S compilation error unable to allocate space for sections/blocks with a total # Welcome to use Markdown editor
I've encountered many strange issues while developing with IAR for STM8, all ...[Details]
Automotive Electronics
京公网安备 11010802033920号
EEWORLD
