IS42S16100E
IS45S16100E
512K Words x 16 Bits x 2 Banks
16Mb SYNCHRONOUS DYNAMIC RAM
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 2048 refresh cycles every 32ms (Com, Ind, A1
grade) or 16ms (A2 grade)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Packages: 400-mil 50-pin TSOP-II and 60-ball
TF-BGA
• Temperature Grades:
Commercial (0
o
C to +70
o
C)
Industrial (-40
o
C to +85
o
C)
Automotive A1 (-40
o
C to +85
o
C)
Automotive A2 (-40
o
C to +105
o
C)
JUNE 2010
DESCRIPTION
ISSI
’s 16Mb Synchronous DRAM IS42/4516100E is
organized as a 524,288-word x 16-bit x 2-bank for
improved performance. The synchronous DRAMs
achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can rea-
sonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
05/18/2010
1
IS42S16100E, IS45S16100E
PIN FUNCTIONS
TSOP Pin No. Symbol
20 to 24
27 to 32
A0-A10
Type
Input Pin
Function (In Detail)
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
command input and A0-A7 as column address inputs during read or write command input.
A10 is also used to determine the precharge mode during other commands. If A10 is
LOW during precharge command, the bank selected by A11 is precharged, but if A10 is
HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically
after the burst access.
These signals become part of the OP CODE during mode register set command input.
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high,
bank 1 is selected. This signal becomes part of the OP CODE during mode register set
command input.
CAS,
in conjunction with the
RAS
and
WE,
forms the device command. See the
“Command Truth Table” item for details on device commands.
The CKE input determines whether the CLK input is enabled within the device. When is
CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid.
When CKE is LOW, the device will be in either the power-down mode, the clock suspend
mode, or the self refresh mode. The CKE is an asynchronous input.
CLK is the master clock input for this device. Except for CKE, all inputs to this device are
acquired in synchronization with the rising edge of this pin.
The CS
input determines whether command input is enabled within the device.
Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when
CS is HIGH.
DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
using the LDQM and UDQM pins.
LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to
the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When
LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be
written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot be
written to the device.
RAS,
in conjunction with
CAS
and
WE,
forms the device command. See the “Command
Truth Table” item for details on device commands.
WE,
in conjunction with
RAS
and
CAS,
forms the device command. See the “Command
Truth Table” item for details on device commands.
VDDQ is the output buffer power supply.
VDD
is the device internal power supply.
GNDQ is the output buffer ground.
GND
is the device internal ground.
19
A11
Input Pin
16
34
CAS
CKE
Input Pin
Input Pin
35
18
CLK
CS
Input Pin
Input Pin
2, 3, 5, 6, 8, 9, 11 DQ0 to
12, 39, 40, 42, 43, DQ15
45, 46, 48, 49
14, 36
LDQM,
UDQM
DQ Pin
Input Pin
17
15
7, 13, 38, 44
1, 25
4, 10, 41, 47
26, 50
RAS
WE
VDDQ
VDD
GNDQ
GND
Input Pin
Input Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
Power Supply Pin
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
05/18/2010
DSP and ARM Processors
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