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8T49N222B-100NLGI8

Description
clock generators & support products femto NG clock generator
Categorysemiconductor    Other integrated circuit (IC)   
File Size683KB,40 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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8T49N222B-100NLGI8 Overview

clock generators & support products femto NG clock generator

8T49N222B-100NLGI8 Parametric

Parameter NameAttribute value
ManufactureIDT (Integrated Device Technology)
Product CategoryClock Generators & Support Products
RoHSYes
TypeClock Translators
Max Input Freq710 MHz
Max Output Freq1200 MHz
Number of Outputs2
Duty Cycle - Max55 %
Operating Supply Voltage2.5 V, 3.3 V
Operating Supply Curre358 mA
Maximum Operating Temperature+ 85 C
Mounting StyleSMD/SMT
Package / CaseVFQFPN-48
Minimum Operating Temperature- 40 C
Output TypeLVPECL, LVDS
PackagingReel
Factory Pack Quantity2000
DATA SHEET
FemtoClock® NG Universal Frequency
Translator
Features
IDT8T49N222I
General Description
The IDT8T49N222I is a highly flexible FemtoClock® NG general
purpose, low phase noise Frequency Translator / Synthesizer with
alarm and monitoring functions suitable for networking and
communications applications. It is able to generate any output
frequency in the 7.29MHz to 833.33MHz range and most output
frequencies in the 925MHz to 1200MHz range (see Table 3A for
details). A wide range of input reference clocks and a range of
low-cost fundamental mode crystal frequencies may be used as the
source for the output frequency.
The IDT8T49N222I has three operating modes to support a very
broad spectrum of applications:
1) Frequency Synthesizer
Fourth generation FemtoClock® NG technology
Universal Frequency Translator
Zero ppm frequency translation
Two outputs, individually programmable as LVPECL or LVDS
Outputs may be individually set to use 2.5V or 3.3V output
levels
Individually programmable output frequencies: 7.29MHz up to
1200MHz
Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 8kHz to 710MHz
Hitless switching between inputs
Crystal input frequency range: 16MHz to 40MHz
Holdover support in the event both inputs fail
One factory-set register configuration for power-up default state
Configurations customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I
2
C
I
2
C Serial interface for register programming
RMS phase jitter at 156.25MHz, using a 40MHz crystal
(12kHz - 20MHz): 507fs (typical), Low Bandwidth Mode (FracN)
Supports ITU-T G.8262 Synchronous Ethernet equipment slave
clocks (EEC option 1 and 2)
Output supply voltage modes:
V
CC
/V
CCA
/V
CCOx
3.3V/3.3V/3.3V
3.3V/3.3V/2.5V (LVPECL only)
2.5V/2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Synthesizes output frequencies from a 16MHz - 40MHz
fundamental mode crystal.
Fractional feedback division is used, so there are no
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy.
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation, so it will not attenuate much jitter on the input
reference.
Applications: Networking & Communications.
Translates any input clock in the 8kHz –710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external crystal to provide
significant jitter attenuation.
2) High-Bandwidth Frequency Translator
3) Low-Bandwidth Frequency Translator
This device provides a factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by the customer and is programmed by
IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured. However, these settings
would have to be written every time the device powers-up.
Pin Assignment
Q0
nQ0
V
EE
OE0
LOCK_IND
V
EE
V
CCO0
nQ1
V
CCO1
V
EE
nc
V
CC
S_AO
S_A1
Reserved
nc
SCLK
SDATA
V
CC
PLL_BYPASS
nc
CLK_ACTIVE
V
EE
LF0
LF1
V
EE
V
EE
nc
V
CCA
HOLDOVER
CLK0BAD
CLK1BAD
XTALBAD
36 35 34 33 32 31 30
29 28 27 26 25
37
24
38
23
39
22
IDT8T49N222I
40
21
48 Lead VFQFN
20
41
7.0mm x 7.0mm x 0.925mm,
42
19
package body
43
18
NL Package
44
17
Top View
45
16
46
15
47
14
48
13
1 2
3
4 5 6 7
8 9
10 11 12
XTAL_OUT
V
CC
CLK_SEL
CLK0
nCLK0
V
CC
nc
V
EE
V
EE
XTAL_IN
CLK1
nCLK1
IDT8T49N222BNLGI REVISION A MAY 13, 2013
1
©2013 Integrated Device Technology, Inc.
OE1
V
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