SI5326B-C-GMR datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> SI5326B-C-GMR

SI5326B-C-GMR: Descriptionclock synthesizer / jitter cleaner precision clk xplier jitter attn 2in/out; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，72 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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SI5326B-C-GMR Overview

clock synthesizer / jitter cleaner precision clk xplier jitter attn 2in/out

SI5326B-C-GMR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Parts packaging code	QFN
package instruction	QFN-36
Contacts	36
Reach Compliance Code	compli
JESD-30 code	S-XQCC-N36
length	6 mm
Humidity sensitivity level	2
Number of terminals	36
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	0.9 mm
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	6 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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Si5326

N Y

-F

R E Q U E N C Y

R E C I S I O N

L O C K

U L T I P LI E R

I T T E R

TTENUATOR

Features



Generates any frequency from 2 kHz



to 945 MHz and select frequencies to

1.4 GHz from an input frequency of



2 kHz to 710 MHz

Ultra-low jitter clock outputs with jitter



generation as low as 0.3 ps rms



(50 kHz–80 MHz)

Integrated loop filter with selectable

loop bandwidth (60 Hz to 8.4 kHz)



Meets OC-192 GR-253-CORE jitter



specifications

Dual clock inputs with manual or

automatically controlled hitless



switching (LVPECL, LVDS, CML,



CMOS)

Dual clock outputs with selectable

signal format

Support for ITU G.709 and custom

FEC ratios (255/238, 255/237,

255/236)

LOL, LOS, FOS alarm outputs

Digitally-controlled output phase

adjustment

C or SPI programmable

On-chip voltage regulator for

1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%

operation

Small size: 6 x 6 mm 36-lead QFN

Pb-free, ROHS compliant

Ordering Information:

See page 65.

Pin Assignments

CKOUT1–

CKOUT2+

CMODE

CKOUT2–

SONET/SDH OC-48/OC-192/STM-

16/STM-64 line cards



ITU G.709 and custom FEC line

cards



GbE/10GbE, 1/2/4/8/10G Fibre

Channel line cards



GbE/10GbE Synchronous Ethernet



Optical modules

Wireless basestations

Data converter clocking

xDSL

PDH clock synthesis

Test and measurement

Broadcast video

GND

36 35 34 33 32 31 30 29 28

RST

INT_C1B

C2B

VDD

GND

10 11 12 13 14 15 16 17 18

CKIN1+

RATE0

RATE1

CKIN2+

CKIN1–

CKIN2–

VDD

LOL

27 SDI

26 A2_SS

25 A1

CKOUT1+

24 A0

23 SDA_SDO

22 SCL

21 CS_CA

20 INC

19 DEC

Applications

VDD

GND

Pad

Description

The Si5326 is a jitter-attenuating precision clock multiplier for applications

requiring sub 1 ps jitter performance. The Si5326 accepts two input clocks ranging

from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz to

945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down

separately from a common source. The Si5326 can also use its crystal oscillator

as a clock source for frequency synthesis. The device provides virtually any

frequency translation combination across this operating range. The Si5326 input

clock frequency and clock multiplication ratio are programmable through an I

C or

SPI interface. The Si5326 is based on Silicon Laboratories' 3rd-generation

DSPLL

technology, which provides frequency synthesis and jitter attenuation in a

highly integrated PLL solution that eliminates the need for external VCXO and

loop filter components. The DSPLL loop bandwidth is digitally programmable,

providing jitter performance optimization at the application level. Operating from a

single 1.8, 2.5, or 3.3 V supply, the Si5326 is ideal for providing clock

multiplication and jitter attenuation in high performance timing applications.

Rev. 1.0 9/10

Si5326

SI5326B-C-GMR Related Products

	SI5326B-C-GMR	Si5326A-C-GM	SI5326A-C-GMR
Description	clock synthesizer / jitter cleaner precision clk xplier jitter attn 2in/out	clock synthesizer / jitter cleaner any-rate clk mult jitter atten 2 outs	clock synthesizer / jitter cleaner precision clk xplier jitter attn 2in/out
Is it Rohs certified?	conform to	conform to	conform to
Maker	Silicon Laboratories Inc	Silicon Laboratories Inc	Silicon Laboratories Inc
Parts packaging code	QFN	QFN	QFN
package instruction	QFN-36	HVQCCN,	QFN-36
Contacts	36	36	36
Reach Compliance Code	compli	compli	compli
JESD-30 code	S-XQCC-N36	S-XQCC-N36	S-XQCC-N36
length	6 mm	6 mm	6 mm
Number of terminals	36	36	36
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	0.9 mm	0.9 mm	0.9 mm
surface mount	YES	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	40	40	40
width	6 mm	6 mm	6 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC
Humidity sensitivity level	2	-	2

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