8T49N205-005NLGI8 datasheet, PDF

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8T49N205-005NLGI8: Descriptionclock generators & support products femto NG clock generator; Categorysemiconductor Other integrated circuit (IC); File Size420KB，9 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/; Environmental Compliance

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8T49N205-005NLGI8 Overview

clock generators & support products femto NG clock generator

8T49N205-005NLGI8 Parametric

Parameter Name	Attribute value
Manufacture	IDT (Integrated Device Technology)
Product Category	Clock Generators & Support Products
RoHS	Yes
Type	Clock Translators
Max Input Freq	710 MHz
Max Output Freq	1300 MHz
Number of Outputs	2
Operating Supply Voltage	2.5 V, 3.3 V
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	VFQFN-40
Minimum Operating Temperature	- 40 C
Output Type	LVPECL, LVDS
Packaging	Reel
Factory Pack Quantity	5000

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FemtoClock

NG Universal Frequency

Translator with Phase Build-Out

IDT8T49N205I

PRELIMINARY PRODUCT BRIEF

This is a product brief and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found

on the last page.

General Description

The IDT8T49N205I is a highly flexible FemtoClock

NG general

purpose, low phase noise Frequency Translator / Synthesizer with

Phase Build-Out (PBO) suitable for networking and communications

applications. It is able to generate any output frequency in the

0.98MHz - 312.5MHz range and most output frequencies in the

312.5MHz - 1,300MHz range (see Table 3 for details). A wide range

of input reference clocks and a range of low-cost fundamental mode

crystal frequencies may be used as the source for the output

frequency.

The IDT8T49N205I has three operating modes to support a very

broad spectrum of applications:

Frequency Synthesizer

Features

•

Fourth Generation FemtoClock

NG technology

Universal Frequency Translator/Frequency Synthesizer

•

Zero ppm frequency translation

Both outputs may be set to use 2.5V or 3.3V output levels

Programmable output frequency: 0.98MHz up to 1,300MHz

Two outputs, individually programmable as LVPECL or LVDS

Two differential inputs support the following input types:

LVPECL, LVDS, LVHSTL, HCSL

Input frequency range: 8kHz - 710MHz

Phase Build-Out minimizes output phase change on switchover

Crystal input frequency range: 16MHz - 40MHz

Two factory-set register configurations for power-up default state

•

Synthesizes output frequencies from a 16MHz - 40MHz

fundamental mode crystal.

Fractional feedback division is used, so there are no

requirements for any specific crystal frequency to produce the

desired output frequency with a high degree of accuracy.

Applications: PCI Express, Computing, General Purpose

Translates any input clock in the 16MHz - 710MHz frequency

range into any supported output frequency.

This mode has a high PLL loop bandwidth in order to track input

reference changes, such as Spread-Spectrum Clock

modulation, so it will not attenuate much jitter on the input

reference.

Applications: Networking & Communications.

Translates any input clock in the 8kHz -710MHz frequency

range into any supported output frequency.

This mode supports PLL loop bandwidths in the 10Hz - 580Hz

range and makes use of an external crystal to provide

significant jitter attenuation.

2) High-Bandwidth Frequency Translator

•

Power-up default configuration pin or register selectable

Configurations customized via One-Time Programmable ROM

Settings may be overwritten after power-up via I

C Serial interface for register programming

RMS phase jitter at 155.52MHz, using a 40MHz crystal

(12kHz - 20MHz): 463fs (typical), Low Bandwidth Mode (FracN)

Output supply voltage modes:

CCA

CCO

3.3V/3.3V/3.3V

3.3V/3.3V/2.5V (LVPECL only)

2.5V/2.5V/2.5V

-40°C to 85°C ambient operating temperature

Available in lead-free (RoHS 6) packaging

3) Low-Bandwidth Frequency Translator

•

This device provides two factory-programmed default power-up

configurations burned into One-Time Programmable (OTP) memory.

The configuration to be used is selected by the CONFIG pin. The two

configurations are specified by the customer and are programmed by

IDT during the final test phase from an on-hand stock of blank

devices. The two configurations may be completely independent of

one another.

One usage example might be to install the device on a line card with

two optional daughter cards: an OC-12 option requiring a 622.08MHz

LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet

option requiring a 125MHz LVPECL clock translated from the same

19.44MHz input reference.

To implement other configurations, these power-up default settings

can be overwritten after power-up using the I

C interface and the

device can be completely reconfigured. However, these settings

would have to be re-written next time the device powers-up.

The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.

Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

IDT8T49N205NLGI REVISION A OCTOBER 11, 2012

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