LOW SKEW, 1-TO-2
LVCMOS / LVTTL FANOUT BUFFER
Data Sheet
8302I
G
ENERAL
D
ESCRIPTION
The 8302I is a low skew, 1-to-2 LVCMOS Fanout Buffer. The
8302I has a single ended clock input. The single ended clock
input accepts LVCMOS or LVTTL input levels. The 8302I features
a pair of LVCMOS outputs. The 8302I is characterized at full
3.3V for input V
DD
, and mixed 3.3V and 2.5V for output operating
supply modes (V
DDO
). Guaranteedoutput and part-to-part skew
c h a r a c t e r i s t i c s m a k e t h e 8 3 0 2 I i d e a l fo r c l o c k
distribution applications demanding well defined performance
and repeatibility.
F
EATURES
• 2 LVCMOS / LVTTL outputs
• LVCMOS / LVTTL clock input accepts LVCMOS
or LVTTL input levels
• Maximum output frequency: 200MHz
• Output skew: 40ps (typical)
• Part-to-part skew: 250ps (typical)
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core, 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
V
DDO
V
DD
CLK
GND
1
2
3
4
8
7
6
5
Q0
GND
V
DDO
Q1
Q0
CLK
Q1
8302I
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A March 4, 2016
8302I Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 6
2
3
4,7
5
8
Name
V
DDO
V
DD
CLK
GND
Q1
Q0
Power
Power
Input
Power
Output
Output
Pulldown
Type
Description
Output supply pins.
Core supply pin.
LVCMOS / LVTTL clock input.
Power supply ground.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
Output Impedance
V
DD
, V
DDO
= 3.465V
V
DD
= 3.465V, V
DDO
= 2.625V
Test Conditions
Minimum
Typical
4
22
16
51
7
Maximum
Units
pF
pF
pF
kΩ
Ω
©2016 Integrated Device Technology, Inc
2
Revision A March 4, 2016
8302I Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
14
5
Units
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
14
5
Units
V
V
mA
mA
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
CLK
CLK
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
50Ω to V
DDO
/2
I
OH
= -100µA
50Ω to V
DDO
/2
I
OL
= 100µA
-5
2.6
2.9
0.5
0.2
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
V
V
©2016 Integrated Device Technology, Inc
3
Revision A March 4, 2016
8302I Data Sheet
T
ABLE
3D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
CLK
CLK
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
50Ω to V
DDO
/2
I
OH
= -100µA
50Ω to V
DDO
/2
I
OL
= 100µA
-5
1.8
2.2
0.5
0.2
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
V
V
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tsk(o)
tsk(pp)
t
R
t
F
odc
Parameter
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
Output Duty Cycle
20% to 80%
20% to 80%
ƒ
≤
133MHz
133MHz < ƒ
≤
200MHz
300
300
45
40
ƒ
≤
200MHz
1.9
2.35
40
250
Test Conditions
Minimum
Typical
Maximum
200
2.8
105
800
800
800
55
60
Units
MHz
ns
ps
ps
ps
ps
%
%
Parameters measured at f
MAX
unless otherwise noted.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
tp
LH
tsk(o)
tsk(pp)
t
R
t
F
odc
Parameter
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
Output Duty Cycle
20% to 80%
20% to 80%
ƒ
≤
133MHz
133MHz < ƒ
≤
200MHz
250
250
45
40
250
ƒ
≤
200MHz
2.3
Test Conditions
Minimum
Typical
Maximum
200
3.3
110
800
650
650
55
60
Units
MHz
ns
ps
ps
ps
ps
%
%
See Table 4A above for notes.
©2016 Integrated Device Technology, Inc
4
Revision A March 4, 2016
8302I Data Sheet
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
S
KEW
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
©2016 Integrated Device Technology, Inc
5
Revision A March 4, 2016
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