SUMMIT
MICROELECTRONICS, Inc.
Dual 10-bit Nonvolatile DAC
In-system Programmable Analog
FEATURES
•
Two 10-bit Nonvolatile DACs
−
INL
±
1LSB
−
DNL:
±
1LSB
•
Programmable Configuration
•
Programmable Power-on Reset Options
−
Recall Full Scale Value
−
Recall Zero Scale Value
−
Recall Mid-Scale Value
−
Recall NV Register Value
•
Tandem or Independent Operation of DACs
•
Power-down mode (short V
OUT
to gnd)
SMP9210 SMP9211 SMP9212
ISPa
™
OVERVIEW
The SMP9210 is a serial input, voltage output, dual
10-bit digital to analog converter. It can operate from
a single +2.7V to +5.5V supply. Internal precision
buffers swing rail-to-rail with an input reference range
from ground to the positive supply.
The SMP9210 integrates two 10-bit DACs and their
associated circuits that include; an enhanced unity
gain operational amplifier output, a 10-bit volatile data
latch, a 10-bit nonvolatile data register and an
industry standard 2-wire serial interface.
BLOCK DIAGRAM
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MICROELECTRONICS, Inc.
PIN DESCRIPTION
GND
is the device ground pin.
V
OUT
is the voltage output of the DACs. It is
buffered by a unity-gain follower that can slew up to
1V/s.
VREFL
is the lower of the voltage reference
inputs. VREFL must be equal to or greater than
ground and less than VREFH.
VREFH
is the higher of the voltage reference
inputs. VREFH must be equal to or less than VCC
and greater than VREFL.
A0, A1
and
A2
are the address inputs to the
SMP9210 serial interface logic. Biasing the address
inputs will determine the device's bus address that is
contained within the serial data stream when
communication over the serial bus.
SCL
is the serial interface clock. It is used to
clock data into and out of the SMP9210. When
writing to the device, data must remain stable while
SCL is HIGH. When reading, data is clocked out of
the SMP9210 on the falling edge of SCL.
SDA
is a bi-directional pin used to transfer data
into and out of the SMP9210.
Pin 8
is a multifunction pin and is in-system
programmable by the customer or it can be
configured by Summit prior to shipment. It can
function as Chip Select input (V
IH
= selected), a
MUTE input (V
IH
= mute) or as a Vref output (1.25V).
Device Operation
The SMP9210 has two, 10-bit, digital to analog
converters that are comprised of a resistor network
that converts 10-bit digital inputs into equivalent
analog output voltages in proportion to the applied
reference voltages. The voltage differential between
the VREFL and VREFH inputs sets the full-scale
output voltage for its respective DAC.
Each DAC has a 10-bit volatile register that
holds the digital value decoded by the DAC into an
analog voltage output. The register can be written
directly via the serial interface, commanded to load
the zero scale value, full scale value or mid-scale
value or recall a preset value stored in a nonvolatile
register.
Each DAC has a 10-bit nonvolatile register that
can hold a 'set-and-forget' value that can be recalled
whenever the device is powered-on.
The SMP9210 also has a nonvolatile
configuration register that is accessible over the 2-
wire bus. The configuration register is used to
SMP9210 SMP9211 SMP9212
select the device type identifier, the function of pin 8
and the DAC power-on state.
Accessing the DACs
The SMP9210 uses the industry standard 2-wire
serial protocol. The bus is designed for two-way,
two-line serial communication between different
integrated circuits. The two lines are the SCL (serial
clock) and SDA (serial data) and both lines must be
tied to the positive supply through a pull-up resistor..
The protocol defines devices as being either masters
or slaves, the SMP9210 will always be a slave in that
it does not initiate any communications or provide a
clock output.
Data transfers are initiated when a master
issues a 'start' condition, which is a high to low
transition on SDA while SCL is high. The start is
immediately followed by an eight bit transmission:
bits 7:1 comprise the device type identifier and bus
device bus address; bit 0 is the read/write bit
indicating the action to follow. If the intended device
receives the byte and recognizes its address it will
return an acknowledge during the 9
th
clock cycle.
Some data transfers will be concluded with a 'stop'
condition, which is a low to high transition on SDA
while SCL is high. Note: a stop condition must be
performed for all nonvolatile write operations.
Addressing Convention
S
T
A
A
0
1
0
1
2
R
T
A
1
A
0
R/
W
A
C
K
The DAC device type identifier default is
0101[b]. In order to accommodate more than eight
devices on a single bus, the device type identifier can
by modified by the end user by writing to the
configuration registers.
The command structure is illustrated in Table 1.
Of special note is the ability to write individually to the
two DACs or write to them in tandem. The first three
commands are three bytes in length and can either
be volatile or nonvolatile.
The 'Zero' commands load all zeroes into the
DAC registers forcing the V
OUT
to VREFL. The 3F
commands load all ones into the DAC registers,
forcing V
OUT
to VREFH. The Recall commands, write
the nonvolatile register value into the DAC registers.
The PD commands connect V
OUT
to GND. These
four commands are all two bytes; the device
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MICROELECTRONICS, Inc.
Table 1. Command Structure.
MSB
7
6
5
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
0
1
1
1
0
0
0
LSB
0
D8
D8
D8
0
1
1
0
1
1
0
1
1
0
1
1
SMP9210 SMP9211 SMP9212
Command
Write DAC1
Write DAC2
Write Both DACS
ZeroDAC1
ZeroDAC2
ZeroBOTH
3FDAC1
3FDAC2
3FBOTH
RecallDAC1
RecallDAC2
RecallBoth
PDDAC1
PDDAC2
PDBOTH
Function
Write 10-bit value to DAC1
Write 10-bit value to DAC2
Write the same 10-bit value to DAC1
and DAC2
Set DAC1 to Zero Scale (V
REFL
)
Set DAC2 to Zero Scale (V
REFL
)
Set DAC1 & DAC2 to Zero Scale (V
REFL
)
Set DAC1 to Full Scale (V
REFL
)
Set DAC2 to Full Scale (V
REFL
)
Set DAC1 & DAC2 to Full Scale (V
REFL
)
Recall E to DAC1
Recall E to DAC2
Recall E to Both DACs
Power Down DAC1 (V
OUT
to GND)
Power Down DAC2 (V
OUT
to GND)
Power Down Both DACs (V
OUT
to GND)
2
2
2
3
dc
dc
dc
1
1
1
1
1
1
dc
dc
dc
dc
dc
dc
2
dc
dc
dc
1
1
1
1
1
1
dc
dc
dc
dc
dc
dc
1
D9
D9
D9
1
0
1
1
0
1
1
0
1
1
0
1
*dc = don't care
type/address byte followed by the command byte.
They are will be enforced with or without a stop being
issued and the new register value is never stored in
the nonvolatile register.
Writing a value to a DAC can either be a write to the
DAC register only or a combined write to both the
DAC Register and its nonvolatile register. They are
identical with the one exception being the register
write does not entail issuing a stop condition;
whereas, the nonvolatile write operation is concluded
with a stop.
The sequence is to issue a start, followed by the
device type and bus address, with the read/write bit
Writing to DACs Data Sequence (Volatile Write)
S
A
t
A
A
A
C
0
1
0
1
0
1
0
0
1
a
2
1
0
K
r
t
Device Type and Bus Address
W
Command
Writing to DACs Data Sequence (Nonvolatile Write)
S
t
A
A
A
A
0
1
0
1
0
1
0
C
a
2
1
0
r
K
t
Command Sequence (
example command shown 3FDAC1
)
S
t
A
A
A
A
0
1
0
1
0
1
C
a
2
1
0
r
K
t
Device Type and Bus Address
W
set to zero. The SMP9210 will respond with an
acknowledge and the master will then issue the
command and follow-on data. In the example below
the write is to DAC1, where the command = 1001[b];
the dc bits are don't care, D9 and D8 are the MSBs of
the DAC value being written. The SMP9210 will then
respond with an acknowledge followed by the master
writing the last eight bits. In the first example shown,
no stop is generated after the SMP9210
acknowledge; therefore, the write is only to the
register. In the second example the SMP9210
acknowledge is followed by a stop; therefore, the
data is written to both the DAC register and to the
nonvolatile register.
d
c
d
c
D
9
D
8
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
0
1
d
c
d
c
D
9
D
8
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
S
t
o
p
1
1
0
1
1
1
0
A
C
K
Command
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