Single Output LNB Supply Voltage Regulator for
Satellite Set-Top Box Applications
ISL9491, ISL9491A
These devices are designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of single antenna
ports. Each device consists of a current-mode boost
converter and a low-noise linear regulator along with the
circuitry required for tone injection and pin controllable
interface. The device makes the total LNB supply design
simple, efficient and compact with low external
component count.
The current-mode boost converters provide the linear
regulator with input voltage that is set to the voltage at
the VOUT pin plus a minimal drop to insure minimum
power dissipation across the internal LDO. This maintains
constant voltage drop across the linear pass element
while permitting adequate voltage range for tone
injection.
The final regulated output voltage is available at the
cathode of the back diode to support the operation of an
antenna port for a single tuner. The outputs can be set to
various voltage level for the desired polarization
reception by means of the logic presented to the VSET0
and VSET1 pins. An EN pin is to be driven high to enable
the outputs for the PWM and linear combination; setting
EN low disables the output, forcing a shutdown mode.
The external modulation input (EXTM) can accept a tone
modulated DiSEqC command and transfer it
symmetrically to the output to meet DiSEqC 1.x protocol.
An external DiSEqC tank circuit can also be implemented
to support DiSEqC 2.x.
ISL9491, ISL9491A
Features
• Single Chip Power Solution
- Operation for 1-Tuner/1-Dish Applications
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with >92% Efficiency
- Pin Controllable Enable and Output
• 2.5V/3.3V/5V Logic Compatible
• FAULT Signal
• DIRECTV SWM Compliant
• VSET Pin to Toggle between Vertical and Horizontal
Polarizations
• External Tone Input
• Internal Overcurrent and Over-Temperature
Protection
• Pb-Free (ROHs Compliant)
Applications
• LNB Power Supply and Control for Satellite Set-Top
Box
Pin Configuration
ISL9491, ISL9491A
(16 LD QFN)
TOP VIEW
FAULT
13
12 ILIMIT
11 TCAP
10 VSET1
9
5
BYPASS
6
VOUT
7
VSENSE
8
SGND
VSET0
EXTM
VSW
14
EN
15
16
VCC
1
2
3
4
Ordering Information
PART
NUMBER
(Note)
ISL9491ERZ*
PART
MARKING
94 91ERZ
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
L16.4x4
L16.4x4
CS
PGND
GATE
-20 to +85 16 Ld QFN
-20 to +85 16 Ld QFN
ISL9491AERZ*
94 91AERZ
*Add “-T” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3
termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures
that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
October 13, 2009
FN6531.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL9491, ISL9491A
Functional Pin Description
SYMBOL
VSW
PGND
CS
SGND
TCAP
BYPASS
VCC
GATE
VOUT
VSENSE
EXTM
VSET0,
VSET1
EN
FAULT
ILIMIT
Input of the linear post-regulator.
Dedicated ground for the output gate driver of respective PWM.
Current sense input; connect the sense resistor R
SC
at this pin for desired peak overcurrent value for the boost
FET.
Small signal ground for the IC.
Capacitor for setting rise and fall time of the output voltage. Typical value is 0.1µF.
Connect a bypass capacitor of 1µF for the internal 5V.
Main power supply to the chip.
This pin connects to the Gate of the Boost FET.
Output voltage for the LNB meant to be connected to the anode of a back diode in series with the LNB output.
This pin provides for a sensing and pull-down function for the VLNB and is meant to be connected to the cathode
of the back diode.
This is an input for externally modulated DiSEqC tone signal, which is transferred symmetrically onto VLNB.
Output voltage selection pins.
When this pin is low, the output is disabled in a low power standby state. Setting EN = 1 enables the output
voltage.
This an open drain output to be pulled up to the logic high through a resistor. A low indicates that the output
voltage is out of regulation.
The ILIMIT is used to set the value of the output current limit from the linear. A resistor from ILIMIT to GND
programs this limit.
FUNCTION
2
FN6531.0
October 13, 2009
ISL9491, ISL9491A
Block Diagram
10
OLF
DCL
OC1
CLK1
OSCILLATOR
9
15
COUNTER
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
PWM
LOGIC
Q
S
VSET1
VSET0
4
GATE
3
PGND
OTF
-
ILIM1
CS
AMP
∑
SLOPE
COMPENSATION
BAND GAP
REF VOLTAGE
BGV
+
-
REF
VOLTAGE
ADJ1
ILIMIT
12
+
THERMAL
SHUTDOWN
2
CS
VREF1
14
6
7
VSW
VOUT
VSENSE
U AND L
FET
DRIVE
VREF2
EN
+
-
TONE
SHAPE/INJ
CKT
1
8
VCC
SGND
ON CHIP
LDO
UVLO
POR
SOFT-START
BYPASS
FAULT
EXTM
16
INT 5V
SOFT-START
EN
5
13
3
TCAP
11
FN6531.0
October 13, 2009
Typical Application Schematic QFN
VIN
2
+
C36
56µF
0
+
1
D9
B230A
EXTM
C35
100µF
0
C31
10µF
0
R20 10kΩ
3.3/5V
EN
FAULT
RTN
0
L8
10µH
16
15
14
VSW
EXTM
EN
C37
1µF
1
0
1
2
3
2
VCC
CS
FAULT 13
BYPASS
6
5
4
SGND
VOUT
TPC6002
Q1
VSENSE
5
6
7
8
4
NOTES:
FN6531.0
October 13, 2009
R18
18Ω
0
U1
ISL9491ER, or TCAP
10KΩ
ISL9491AER
10
3
PGND
VSET1
9
4
VSET0
GATE
ILIMIT
12
R21 91.1kΩ
0
C40
11R23 0.22µF
D11
B230A
ISL9491, ISL9491A
VSET1
VSET0
DISEqC
FET On
R22
R17
470Ω
R16
0.100Ω
VBYPASS
C39
1µF
C34
100pF
0
0
D12
B230A
15Ω
L2
220µH
C41
0.1µF
R19
3.3kΩ
C42
0.1µF
D10
1.5SMC22A
VLNB
RTN
0
1. The output voltage level for the desired polarization reception can be selected by means of the logic presented to VSET0 and
VSET1 pins.
ISL9491, ISL9491A
Absolute Maximum Ratings
VCC (Input Voltage) . . . . . . . . .
VOUT, VSW . . . . . . . . . . . . . . . .
BYPASS . . . . . . . . . . . . . . . . . . .
EN, VSET0/1, EXTM (Logic Control
All Pins Referenced to Ground
....
....
....
Pins)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
8.0V to 18.0V
-0.3V to 24V
-0.3V to 5.5V
-0.3V to 5.5V
Thermal Information
Thermal Resistance (Typical)
θ
JA
(°C/W)
θ
JC
(°C/W)
QFN Package (Notes 2, 3) . . . . . . .
47
9.5
Maximum Junction Temperature (Note 4) . . . . . . . +150°C
Maximum Storage Temperature Range . . . -40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature. . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
2.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
3. For
θ
JC
, the "case temp" location is the center of the exposed metal pad on the package underside.
4. The device junction temperature should be kept below +150°C. Thermal shut-down circuitry turns off the device if junction
temperature exceeds +130°C typical.
Electrical Specifications
PARAMETER
Operating Supply Voltage Range
V
CC
= 12V, T
A
= -20°C to +85°C, unless otherwise noted. Typical values are at
T
A
= +25°C.
SYMBOL
ISL9491
ISL9491A
TEST CONDITIONS
MIN
8
8
-
TYP
12
10
4
MAX
14
11
8
UNITS
V
V
mA
Supply Current (Ivcc current)
I
IN
EN = 1, Boost disconnected, and ext. 14.5V
supply on VSW when V
OUT
= 13.3V,
No Load
UNDERVOLTAGE LOCKOUT
Stop Threshold
Start Threshold
Output Voltage, ISL9491
V
O
Input voltage falling from above 8V
Input voltage rising from 0V
EN = 1, VSET1 = 0, VSET0 = 0
EN = 1, VSET1 = 0, VSET0 = 1
EN = 1, VSET1 = 1, VSET0 = 0
EN = 1, VSET1 = 1, VSET0 = 1
Output Voltage, ISL9491A
V
O
EN = 1, VSET1 = 0, VSET0 = 0
EN = 1, VSET1 = 0, VSET0 = 1
EN = 1, VSET1 = 1, VSET0 = 0
EN = 1, VSET1 = 1, VSET0 = 1
Line Regulation
DV
O1,
DV
O2
DV
O1,
DV
O2
V
IN
= 8V to 14V; V
O
= 13.30V
V
IN
= 8V to 14V; V
O
= 18.30V
I
O
= 0mA to 350mA, V
OUT
= 13.3V
I
O
= 0mA to 500mA, V
OUT
= 13.3V
(Note 4)
R at I
LIMIT
= 148k (Note 8)
Output Shorted to GND, R
ILIM
= 0
-
-
12.8
17.7
13.8
19.4
10.5
14.5
11.5
15.5
-
-
-
-
270
4.4
4.9
13.3
18.3
14.3
20.0
11.0
15.0
12.0
16.0
4
4
125
190
350
-
-
13.6
18.7
14.6
20.4
11.3
15.3
12.3
16.3
40
60
180
260
435
860
V
V
V
V
V
V
V
V
V
V
mV
mV
mV
mV
mA
mA
Load Regulation
Output Overcurrent Threshold
Internal Regulator Overcurrent
Clamp
I
OCT
I
OCLMP
5
FN6531.0
October 13, 2009
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