LSI/CSI
UL
®
LS8297
LS8297CT
(631) 271-0400 FAX (631) 271-0405
April 2009
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
A3800
STEPPER MOTOR CONTROLLER
FEATURES:
• Controls Bipolar and Unipolar Motors
• Cost-effective,
low current,
pin compatible replacement for
L297
• Torque ripple compensated half-steps
- LS8297CT
• Half and full step modes
• Normal/wave drive
• Direction control
• Reset input
• Step control input
• Enable input
• PWM chopper circuit for current control
• Two over current sensor comparators with external references input
• All inputs and outputs TTL/CMOS compatible (TTL for 5V operation)
•
Supply current < 400uA
• 4.75 to 7V Operation (V
DD
– V
SS
).
•
LS8297
(DIP),
LS8297-S
(SOIC),
LS8297-TS
(TSSOP)
LS8297CT
(DIP),
LS8297CT-S
(SOIC),
LS8297CT-TS
(TSSOP)
– See Figure 1 –
DESCRIPTION:
The
LS8297
Stepper Motor Controller generates four phase drive signal
outputs for controlling two phase Bipolar and four phase Unipolar mo-
tors. The outputs are used to drive two H-bridges for the two motor
windings in the Bipolar motor or the four driver transistors for the two
center- tapped windings in the Unipolar motor. The motor can be driven
in full step mode either in normal drive (two-phase-on) or wave drive
(one-phase-on) and half step mode. The
LS8297
provides two inhibit
outputs which are used to control the driver stages of each of the motor
phases. The circuit uses STEP, FRD/REV and HALF/FULL inputs in a
translator to generate controls for the output stages.
A dual PWM chopper circuit using an on-chip oscillator, latches and volt-
age comparators are used to regulate the current in the motor windings.
For each pair of phase driver outputs (PHA, PHB, and PHC, PHD) each
pulse of the common internal oscillator sets the latch and enables the
output. If the current in the motor winding causes the voltage across a
sense resistor to exceed the reference voltage, V
REF
, at the comparator
inputs, the latch is reset disabling the output until the next oscillator
pulse.
The CONTROL input determines whether the chopper acts on the
phase driver outputs or the inhibit outputs. When the phase lines are
chopped, the non-active phase line of each pair (PHA, PHB or PHC,
PHD) is activated rather than de-activating the active line to reduce dis-
sipation in the load sensing resistors. Refer to Figure 5B for Bipolar mo-
tors. If PHA is high and PHB is low, current flows through Q1, motor
winding, Q4 and sense resistor Rs. When chopping occurs, PHB is
brought high and circulating current flows through Q1 and D3 and not
through Rs resulting in less power dissipation in Rs. Current decay is
slow using this method. When the Control input is brought low, chopping
occurs by bringing INH1 low. In this case circulating current flows
through D2, motor winding and D3 and through the power supply to
ground causing the current to decay rapidly. For Unipolar motors, only
inhibit chopping is used. Refer to Figure 6. When INH1 is brought low
8297-042009-1
PIN ASSIGNMENT
TOP VIEW
20
19
18
17
LS8297
LS8297CT
SYNC
V
SS
HOME
PHA
INH1
PHB
PHC
INH2
PHD
ENABLE
1
2
3
4
5
6
7
8
9
10
RESET
HALF/FULL
STEP
FWD/REV
OSC
VREF
SENSE1
SENSE2
V
DD
CONTROL
current in either half of the center tapped motor winding recir-
culates through the diode across it.
LS8297CT
is the torque ripple compensated version of the
LS8297.
Torque imbalance resulting from alternating “one-
phase on”, “two-phase on” sequence of the half-step mode
(see Figure 4) is eliminated in the
LS8297CT
by switching the
sense reference voltage between 100% and 70.7% in alter-
nate steps.
INPUT/OUTPUT DESCRIPTION:
OSC Input
An RC input with the resistor connected to V
DD
and the ca-
pacitor connected to ground determines the oscillator chopper
rate. When connected as an oscillator, the oscillator output
appears as a negative-going pulse at the Sync pin. If the Os-
cillator pin is tied to ground, the Sync pin becomes an input.
Osc frequency, fosc = 1/0.69RC
SYNC
As an output the Sync can be used to drive Sync pins of other
LS8297s.
This eliminates the need for RC components for
any other
LS8297
controllers used in the system. As an input
the Sync can be driven by the
LS8297
that has the RC oscilla-
tor components or by any other system external clock.
LSI
16
15
14
13
12
11
FIGURE 1
PHA/PHB/PHC/PHD
Phase drive output signals for power stages. In a Bipolar motor
PHA and PHB are used for one H-bridge while PHC and PHD
are used for the other.
INH1/INH2 Outputs
These outputs are active low inhibit controls for motor drive
outputs. INH1 controls driver stage using PHA and PHB sig-
nals while INH2 control driver stage using PHC and PHD sig-
nals. When the Control input is low, these outputs are chopped
using the internal oscillator for current regulating.
CONTROL Input
When high, the phase outputs, PHA, PHB, PHC and PHD are
chopped. When low, INH1 and INH2 are chopped. Normally,
inhibit outputs are chopped. Phase chopping might be used
with a Bipolar motor that does not store much energy to pre-
vent fast current decay and a low useful torque.
ENABLE Input
When Enable input is low, INH1, INH2, PHA, PHB, PHC and
PHD are brought low.
HOME Output
An open drain output that indicates when the
LS8297
is in its
initial state with PHA, PHB, PHC, PHD = logic states 0101 re-
spectively. Refer to Figure 4. In the active state the open drain
device is off.
STEP Input
An active low pulse on this input causes the motor to ad-
vance one step. The step occurs on the rising edge of the
step signal.
FRD/REV Input
A logic 1 on this input causes the motor to advance through
the stepping sequence of Fig. 4. A logic 0 on this input cause
the motor to reverse the sequence.
RESET Input
An active low on this input cause the motor to be restored to
the home position (0101).
HALF/FULL Input
When high, half-step operation is selected. When low, full-
step operation is selected. One-phase on full step is selected
by selecting full when stepping sequence is at an even state.
Two-phase on full step operation is selected when stepping
sequence is at an odd state. Refer to Figure 4.
SENSE1/ SENSE2 Inputs
Inputs for load current sense voltages from power stages us-
ing PHA and PHB drive signals or PHC and PHD drive sig-
nals, respectively.
V
REF
Reference voltage for chopper circuit which determines the
peak load current.
V
DD
12
V
SS
2
PHA INH1 PHB PHC INH2
4
5
6
7
8
PHD
9
+V
19
20
17
HALF/FULL
RESET
FWD/REV
10
ENABLE
TRANSLATOR
OUTPUT LOGIC
11
CONTROL
STEP
18
Q S
FF1
R
Q
FF2
R
1
OSC
SYNC
S
x0.707
HOME
3
MUX
+
-
+
-
15
V
REF
14
SENSE1
13
SENSE2
16
OSC
FIGURE 2. LS8297/LS8297CT BLOCK DIAGRAM
8297-091608-2
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