®
X9279
Single Supply/Low Power/256-Tap/2-Wire Bus
Data Sheet
September 23, 2009
FN8175.4
Single Digitally-Controlled (XDCP™)
Potentiometer
The X9279 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using
255 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-Wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• 256 Resistor Taps
• 2-Wire Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
• Wiper Resistance, 100Ω Typical @ 5V
• 16 Non-volatile Data Registers for Each Potentiometer
• Non-volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
Power-up.
• Standby Current < 5µA Max
• V
CC
: 2.7V to 5.5V Operation
• 50kΩ, 100kΩ Versions of End-to-End Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 yr. Data Retention
• 14 Ld TSSOP
• Low Power CMOS
• Pb-Free Available (RoHS Compliant)
Functional Diagram
V
CC
R
H
2-WIRE
BUS
INTERFACE
ADDRESS
DATA
STATUS
BUS
INTERFACE
AND
CONTROL
WRITE
READ
TRANSFER
INC/DEC
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
16 BYTES
WIPER
50kΩ and 100kΩ
256-TAPS
POT
CONTROL
V
SS
R
W
R
L
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9279
Ordering Information
PART
NUMBER
X9279TV14* (Note 2)
X9279TV14Z*
(Note 1)
X9279TV14I* (Note 2)
X9279TV14IZ*
(Note 1)
X9279UV14*
(Note 2)
X9279UV14Z*
(Note 1)
X9279UV14I*
(Note 2)
X9279UV14IZ*
(Note 1)
X9279TV14-2.7*
(Note 2)
X9279TV14Z-2.7*
(Note 1)
X9279TV14I-2.7*
(Note 2)
X9279TV14IZ-2.7*
(Note 1)
X9279UV14-2.7*
(Note 2)
X9279UV14Z-2.7*
(Note 1)
X9279UV14I-2.7*
(Note 2)
X9279UV14IZ-2.7*
(Note 1)
PART
MARKING
X9279 TV
X9279 TVZ
X9279 TVI
X9279 TVZI
X9279 UV
X9279 UVZ
X9279 UVI
X9279 UVZI
X9279 TVF
X9279 TVZF
X9279 TVG
X9279 TVZG
X9279 UVF
X9279 UVZF
X9279 UVG
X9279 UVZG
50
2.7 to 5.5
100
50
V
CC
LIMITS
(V)
5 ±10%
POTENTIOMETER
ORGANIZATION
(kΩ)
100
TEMP RANGE
(°C)
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
PACKAGE
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
(Pb-free)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
(Pb-free)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
(Pb-free)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
(Pb-free)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
(Pb-free)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
(Pb-free)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
(Pb-free)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
(Pb-free)
PKG.
DWG. #
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Not recommended for new designs.
2
FN8175.4
September 23, 2009
X9279
Detailed Functional Diagram
V
CC
BANK 0 POWER-ON RECALL
DR0 DR1
WIPER
COUNTER
REGISTER
(WCR)
50kΩ and 100kΩ
256-TAPS
R
L
R
W
R
H
SCL
SDA
A3
A2
A1
A0
WP
INTERFACE
AND
CONTROL
CIRCUITRY
D ATA
DR2 DR3
BANK 1
DR0 DR1
BANK 2
DR0 DR1
BANK 3
DR0 DR1
DR2 DR3
CONTROL
DR2 DR3
DR2 DR3
12 ADDITIONAL NON-VOLATILE REGISTERS
3 BANKS OF 4 REGISTERS x 8-BITS
V
SS
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable DC reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in
filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent systems
3
FN8175.4
September 23, 2009
X9279
Pinout
X9279
(14 LD TSSOP)
TOP VIEW
NC
A0
NC
A2
SCL
SDA
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
R
L
R
H
R
W
A3
A1
WP
connected to ground for proper operation. A match in the slave
address serial data stream must be made with the Address
input in order to initiate communication with the X9279. A
maximum of 8 devices may occupy the 2-Wire serial bus.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Pin Functions
PIN
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYMBOL
NC
A0
NC
A2
SCL
SDA
V
SS
WP
A1
A3
R
W
R
H
R
L
V
CC
No Connect
Device Address for 2-Wire bus
No Connect
Device Address for 2-Wire bus
Serial Clock for 2-Wire bus
Serial Data Input/Output for 2-Wire bus
System Ground
Hardware Write Protect
Device Address for 2-Wire bus
Device Address for 2 wire-bus. Must be
connected to Ground
Wiper Terminal of the Potentiometer
High Terminal of the Potentiometer
Low Terminal of the Potentiometer
System Supply Voltage
FUNCTION
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is
the system ground.
Other Pins
NO CONNECT
No connect pins should be left open. This pins are used for
Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents non-volatile writes to the
Data Registers.
Principles Of Operation
The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter and the
serial interface logic providing direct communication
between the host and the digitally controlled potentiometers.
This section provides detail description of the following:
• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description
Pin Descriptions
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for a
2-Wire slave device and is used to transfer data into and out
of the device. It receives device address, opcode, wiper
register address and data sent from an 2-Wire master at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock SCL.
It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
SERIAL CLOCK (SCL)
This input is used by 2-Wire master to supply 2-Wire serial
clock to the X9279.
DEVICE ADDRESS (A3 - A0)
The Address inputs A2 - A0 are used to set the least significant
3 bits of the 8-bit slave address, address pin A3 must be
Array Description
The X9279 is comprised of a resistor array (see Figure 1).
The array contains, in effect, 255 discrete resistive segments
that are connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R
W
)
output. Within each individual array only one switch may be
turned on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to
select, and enable, one of 256 switches (see Table 1).
The WCR may be written directly. These Data Registers can
the WCR can be read and written by the host system.
FN8175.4
September 23, 2009
4
X9279
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
8
BANK_0 Only
SERIAL
BUS
INPUT
REGISTER 1
(DR1)
8
PARALLEL
BUS
INPUT
C
O
U
N
T
E
R
D
E
C
O
D
E
R
R
H
REGISTER 2
(DR2)
REGISTER 3
(DR3)
WIPER
COUNTER
REGISTER
(WCR)
IF WCR = 00[H] THEN R
W
= R
L
IF WCR = FF[H] THEN R
W
= R
H
INC/DEC
LOGIC
UP/DN
MODIFIED SCK
UP/DN
CLK
R
L
R
W
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Power-up and Down Recommendations.
There are no restrictions on the power-up or power-down
conditions of V
CC
and the voltages applied to the
potentiometer pins provided that V
CC
is always more
positive than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
≥
V
H
, V
L
,
V
W
. The V
CC
ramp rate specification is always in effect.
Start Condition
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9279 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met (see Figure 2).
Serial Interface Description
Serial Interface
The X9279 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9279 will be
considered a slave device in all applications.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 2).
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9279 will
respond with a final acknowledge (see Figure 2).
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (see
Figure 2.
5
FN8175.4
September 23, 2009
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