– Provides device-specific information to the system, allowing host
software to easily reconfigure for different Flash devices
Sector Group Protection Features
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Group Unprotect feature allows code changes in
previously locked sectors
Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or program data to,
a sector that is not being erased, then resumes the erase operation
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase operation
completion
Top or Bottom Boot Block Configurations Available
Compatibility with JEDEC standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
Performance Characteristics
High Performance
– Access times as fast as 70 ns
– Industrial temperature range (-40°C to +85°C)
– Word programming time as fast as 6 µs (typical)
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
WP# input pin
– Write protect (WP#) function allows protection of two outermost
boot sectors (boot sector models only), regardless of sector group
protect status
Publication Number
S29AS008J_00
Revision
09
Issue Date
November 9, 2011
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient pro-
duction volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid com-
binations offered may occur.
D at a
S hee t
General Description
The S29AS008J is a 8 Mbit, 1.8 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words with
a x8/x16 bus and either top or bottom boot sector architecture. The device is offered in 48-pin TSOP and 48-
ball FBGA packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on
DQ7–DQ0. This device is designed to be programmed and erased in-system with the standard system 1.8
volt V
CC
supply. A 12.0 V V
PP
or 5.0 V
CC
are not required for program or erase operations. The device can
also be programmed in standard EPROM programmers.
The device offers access time of 70 ns allowing high speed microprocessors to operate without wait states. To
eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
The device requires only a
single 1.8 volt power supply
for both read and write functions. Internally
generated and regulated voltages are provided for the program and erase operations.
The S29AS008J is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using standard microprocessor write timings. Register
contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations. Reading
data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facilitates faster programming times by requiring only two write
cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin,
or by reading the DQ7 (Data# Polling) and DQ6 (toggle)
status bits.
After a program or erase cycle has been
completed, the device is ready to read array data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The
hardware sector group protection
feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is not selected for erasure. True background erase can
thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron
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