1:1 Differential-to-LVDS Zero Delay
Clock Generator
Data Sheet
874S02I
General Description
The 874S02I is a highly versatile 1:1 Differential- to-LVDS Clock
Generator and a member of the family of High Performance Clock
Solutions from IDT. The 874S02I has a fully integrated PLL and
can be configured as a zero delay buffer, multiplier or divider, and
has an output frequency range of 62.5MHz to 1GHz. The
reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the
input clock and the output clocks. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
One differential LVDS output pair and
one differential feedback output pair
One differential clock input pair
CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL
Input frequency range: 62.5MHz to 1GHz
Output frequency range: 62.5MHz to 1GHz
VCO range: 500MHz - 1GHz
External feedback for "zero delay" clock regeneration with
configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 35ps (maximum)
Static phase offset: ±100ps
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free packages
Block Diagram
PLL_SEL
Pullup
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
Pin Assignment
0
1
Q
nQ
QFB
nQFB
CLK
nCLK
MR
nFB_IN
FB_IN
SEL2
V
DDO
nQFB
QFB
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SEL1
SEL0
V
DD
PLL_SEL
V
DDA
SEL3
GND
Q
nQ
V
DDO
CLK
Pulldown
nCLK
Pullup
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
FB_IN
Pulldown
nFB_IN
Pullup
874S02I
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
SEL0
Pulldown
SEL1
Pulldown
SEL2
Pulldown
SEL3
Pulldown
MR
Pulldown
©2016 Integrated Device Technology, Inc
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January 26, 2016
874S02I Data Sheet
Table 1. Pin Descriptions
Number
1
2
Name
CLK
nCLK
Input
Input
Type
Pulldown
Pullup
Description
Non-inverting differential clock input.
Inverting differential clock input.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q and QFB to go low and the inverted outputs nQ and
nQFB to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.” Connect to pin 8.
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.” Connect to pin 9.
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
Output supply pins.
Differential feedback output pair. HSTL interface levels.
Power supply ground.
Differential clock output pair. HSTL interface levels.
Analog supply pin.
Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
Core supply pin.
3
MR
Input
Pulldown
4
5
6, 15,
19, 20
7, 11
8, 9
10, 14
12, 13
16
17
18
nFB_IN
FB_IN
SEL2, SEL3,
SEL0, SEL1
V
DDO
nQFB, QFB
GND
nQ, Q
V
DDA
PLL_SEL
V
DD
Input
Input
Input
Power
Output
Power
Output
Power
Input
Power
Pullup
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
50
50
Maximum
Units
pF
k
k
R
PULLDOWN
Input Pulldown Resistor
©2016 Integrated Device Technology, Inc
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January 26, 2016
874S02I Data Sheet
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
Reference Frequency Range (MHz)*
500 - 1000
250 - 500
125 - 250
62.5 - 125
500 - 1000
250 - 500
125 - 250
500 - 1000
250 - 500
500 - 1000
250 - 500
125 - 250
62.5 - 125
125 - 250
62.5 - 125
62.5 - 125
Q/nQ
÷1
÷1
÷1
÷1
÷2
÷2
÷2
÷4
÷4
÷8
x2
x2
x2
x4
x4
x8
SEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*NOTE: VCO frequency range for all configurations above is 500MHz to 1GHz.
©2016 Integrated Device Technology, Inc
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January 26, 2016
874S02I Data Sheet
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Q/nQ
÷4
÷4
÷4
÷8
÷8
÷8
÷16
÷16
÷32
÷64
÷2
÷2
÷4
÷1
÷2
÷1
SEL3
0z
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
©2016 Integrated Device Technology, Inc
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January 26, 2016
874S02I Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
64.7°C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.20
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
97
20
40
Units
V
V
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
MR, SEL[0:3]
Input High Current
PLL_SEL
MR, SEL[0:3]
I
IL
Input Low Current
PLL_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-10
-150
Test Conditions
Minimum
2.2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
10
Units
V
V
µA
µA
µA
µA
©2016 Integrated Device Technology, Inc
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January 26, 2016
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