Si8716BC-A-IP datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> Si8716BC-A-IP

Si8716BC-A-IP: Descriptiondigital isolators 3.75 kV opto Hi-cmti inverting output; CategoryAnalog mixed-signal IC The signal circuit; File Size2MB，35 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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digital isolators 3.75 kV opto Hi-cmti inverting output

Si8716BC-A-IP Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	compli
Analog Integrated Circuits - Other Types	ANALOG CIRCUIT

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S i 8 7 1 x /2 x



L E D E

MU LAT OR

NPUT

, L

O G I C

UTPUT

SOLATORS

Wide range of product options



Inverting and non-inverting



Disable output high, low or tri-state

1 channel diode emulator input

Propagation delay 30 ns

Up to 5000 V

RMS

isolation

10 kV surge withstand capability

AEC-Q100 qualified

Wide operating temperature range



– 40 to +125 °C

RoHS-compliant packages



SOIC-8 (Narrow body)



DIP8 (Gull-wing)



SDIP6 (Stretched SO-6)

Features

High Speed: dc to 15 Mbps



2.5 to 5.5 V logic output



Pin-compatible, drop-in upgrades for

popular high-speed digital



optocouplers



Performance and reliability



advantages vs. optocouplers





Resistant to temperature, age and



forward current effects





10x lower FIT rate for longer

service life





Higher common-mode transient

immunity: >50 kV/µs typical



Lower power and forward input

diode current

Pin Assignments:

See page 21

UVLO

VDD

ANODE

CATHODE

GND

SOIC-8, DIP8

Industry Standard Pinout

UVLO

Applications

Industrial automation



Isolated data acquisition



Motor controls and drives



Test and measurement equipment



Isolated switch mode power supplies



VDD

ANODE

CATHODE

GND

Safety Regulatory Approvals (Pending)



UL 1577 recognized





VDE certification conformity



IEC60747-5-2/VDE0884-10

CSA component notice 5A

approval



IEC

to 5000 Vrms for 1 minute



CQC certification approval



GB4943.1

(basic/reinforced insulation)

SOIC-8, DIP8 with Output Enable

Industry Standard Pinout

60950-1, 61010-1, 60601-1

(reinforced insulation)

ANODE 1

NC 2

UVLO

VDD

Description

The Si871x/2x isolators are pin-compatible, single-channel, drop-in

replacements for popular optocouplers with data rates up to 15 Mbps.

These devices isolate high-speed digital signals and offer performance,

reliability, and flexibility advantages not available with optocoupler

solutions. The Si871x/2x series is based on Silicon Labs' proprietary

CMOS isolation technology for low-power and high-speed operation and

are resistant to the wear-out effects found in optocouplers that degrade

performance with increasing temperature, forward current, and device

age. As a result, the Si871x/2x series offer longer service life and

dramatically higher reliability compared to optocouplers. Ordering options

include logic output with and without output enable options.

CATHODE 3

GND

SDIP6

Industry Standard Pinout

Patent pending

Rev. 1.0 8/14

Si871x/2x

Si871x/2x

ABLE

Section

ONTENTS

Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.3. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2. Output Circuit Design and Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . 18

5. Pin Descriptions (SOIC-8, DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6. Pin Descriptions (SOIC-8, DIP8) with Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7. Pin Descriptions (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

12. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

13. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

14. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

15. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15.1. Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15.2. Top Marking Explanation (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . 31

15.3. Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

15.4. Top Marking Explanation (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

15.5. Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

15.6. Top Marking Explanation (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Rev. 1.0

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