19-2397; Rev 0; 4/02
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
General Description
The MAX9381 differential data, differential clock D flip-
flop is pin compatible with the ON Semiconductor
MC100EP52, with the added benefit of a wider supply-
voltage range from 2.25V to 5.5V and 25% lower supply
current. Data enters the master part of the flip-flop
when the clock is low and is transferred to the outputs
upon a positive transition of the clock. Interchanging
the clock inputs allows the part to be used as a nega-
tive edge-triggered device. The MAX9381 utilizes input
clamping circuits that ensure the stability of the outputs
when the inputs are left open or at V
EE
.
The MAX9381 is offered in an 8-pin SO package and
the smaller 8-pin µMAX package.
o
0.2ps
RMS
Added Random Jitter
o
328ps Typical Propagation Delay
o
PECL Operation from V
CC
= 2.25V to 5.5V with
V
EE
= 0V
o
ECL Operation from V
EE
= -2.25V to -5.5V with
V
CC
= 0V
o
Input Safety Clamps Ensure Output Stability when
Inputs are Open or at V
EE
o
±2kV ESD Protection (Human Body Model)
Features
o
3.0GHz Guaranteed Operating Clock Frequency
MAX9381
Applications
Precision Clock and Data Distribution
Central Office
DSLAM
DLC
Base Station
ATE
PART
MAX9381ESA
MAX9381EUA*
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 SO
8 µMAX
*Future
product—contact factory for availability.
Functional Diagram
TOP VIEW
Pin Configuration
MAX9381
D
1
8
V
CC
D
D
Q
CLK
CLK
3
Q
6
Q
3
1
2
8
7
V
CC
Q
Q
V
EE
D
2
75kΩ
75kΩ
D
Q
7
MAX9381
6
5
CLK
4
CLK
4
75kΩ
75kΩ
5
SO/µMAX
V
EE
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
MAX9381
ABSOLUTE MAXIMUM RATINGS
V
CC
- V
EE
...............................................................-0.3V to +6.0V
Input Voltage (D,
D,
CLK,
CLK)
.......(V
EE
- 0.3V) to (V
CC
+ 0.3V)
Differential Input Voltage ...............Smaller of |V
CC
- V
EE
| or 3.0V
Output Current (Q,
Q)
Continuous .......................................................................50mA
Surge..............................................................................100mA
Junction-to-Ambient Thermal Resistance in Still Air
8-Pin µMAX ..............................................................+221°C/W
8-Pin SO ...................................................................+170°C/W
Maximum Continuous Power Dissipation
8-Pin µMAX (derate 4.5mW/°C above +70°C) ..............362mW
8-Pin SO (derate 5.9mW/°C above +70°C)...................471mW
Junction-to-Ambient Thermal Resistance with
500LFPM Airflow
8-Pin µMAX ..............................................................+155°C/W
8-Pin SO .....................................................................+99°C/W
Junction-to-Case Thermal Resistance
8-Pin µMAX ................................................................+39°C/W
8-Pin SO .....................................................................+40°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
ESD Protection
Human Body Model ..........................................................±2kV
Soldering Temperature (10s) ...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= 2.25V to 5.5V (T
A
= +25°C to +85°C), V
CC
- V
EE
= 2.375V to 5.5V (T
A
= -40°C to +25°C), outputs terminated with 50Ω
±1% to V
CC
- 2.0V, unless otherwise noted. Typical values are at V
CC
- V
EE
= 3.3V, V
IHD
= V
CC
- 1.0V, V
ILD
= V
CC
- 1.5V, unless oth-
erwise noted.) (Notes 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
-40°C
MIN
V
EE
+
1.2
V
EE
V
CC
- V
EE
< 3.0V
V
ID
Figure 1
V
CC
- V
EE
≥
3.0V
D,
D,
CLK, or CLK
= V
IHD
or V
ILD
0.15
-10
0.15
TYP
MAX
MIN
V
EE
+
1.2
V
EE
0.15
0.15
-10
+25°C
TYP
MAX
MIN
V
EE
+
1.2
V
EE
0.15
0.15
-10
+85°C
TYP
MAX
UNITS
INPUTS (D,
D,
CLK,
CLK)
Differential Input
High Voltage
Differential Input
Low Voltage
V
IHD
V
ILD
Figure 1
Figure 1
V
CC
V
CC
-
0.15
V
CC
-
V
EE
3.0
+200
V
CC
V
CC
-
0.15
V
CC
-
V
EE
3.0
+200
V
CC
V
CC
-
0.15
V
CC
-
V
EE
3.0
+200
µA
V
V
Differential Input
Voltage
V
Single-Ended
Input Current
OUTPUTS (Q,
Q)
Output High
Voltage
Output Low
Voltage
Differential
Output Voltage
POWER SUPPLY
Power-Supply
Current (Note 4)
I
IH
, I
IL
V
OH
V
OL
V
OD
Figure 1
Figure 1
V
OH
- V
OL
,
Figure 1
V
CC
-
1.145
V
CC
-
1.945
550
V
CC
-
0.895
V
CC
-
1.695
V
CC
-
1.145
V
CC
-
1.945
550
V
CC
-
0.895
V
CC
-
1.695
V
CC
-
1.145
V
CC
-
1.945
550
V
CC
-
0.895
V
CC
-
1.695
V
V
mV
I
EE
17
35
20
35
22
35
mA
2
_______________________________________________________________________________________
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
AC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= 2.25V to 5.5V (T
A
= +25°C to +85°C), V
CC
- V
EE
= 2.375V to 5.5V (T
A
= -40°C to +25°C), outputs terminated with 50Ω
±1% to V
CC
- 2.0V, f
CLK
≤
3.0GHz, input transition time = 125ps (20% to 80%), V
IHD
= V
EE
+ 1.2V to V
CC
, V
ILD
= V
EE
to V
CC
- 0.15V,
V
IHD
- V
ILD
= 0.15V to smaller of |V
CC
- V
EE
| or 3V, unless otherwise noted. Typical values are at V
CC
- V
EE
= 3.3V, V
IHD
= V
CC
- 1.0V,
V
ILD
= V
CC
- 1.5V, unless otherwise noted.) (Notes 1, 5)
PARAMETER
Propagation Delay
CLK,
CLK
to Q,
Q
Maximum Clock
Frequency
Setup Time
Hold Time
Added Random
Jitter (Note 6)
Differential Output
Rise/Fall Time
SYMBOL
t
PHL
t
PLH
f
CLKMAX
t
S
t
H
t
RJ
t
R
/t
F
20% to 80%,
Figure 2
70
CONDITIONS
Figure 2
V
OD
≥
300mV
Figure 2
Figure 2
3.0
100
50
0.2
120
0.8
170
80
-40°C
MIN
TYP
MAX
370
3.0
100
50
0.2
120
0.8
180
90
MIN
+25°C
TYP
328
MAX
405
3.0
100
50
0.2
120
0.8
200
MIN
+85°C
TYP
MAX
490
UNITS
ps
GHz
ps
ps
ps
(RMS)
ps
MAX9381
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters are production tested at +25°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4:
All pins floating except V
CC
and V
EE
.
Note 5:
Guaranteed by design and characterization, and are not production tested. Limits are set to ±6 sigma.
Note 6:
Device jitter added to the input clock.
_______________________________________________________________________________________
3
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
MAX9381
Typical Operating Characteristics
(V
CC
- V
EE
= 3.3V, outputs loaded with 50Ω ±1% to V
CC
- 2V, V
IH
= V
CC
- 1V, V
IL
= V
CC
- 1.5V, f
CLK
= 3GHz, f
D
= f
CLK
/2 input tran-
sition time = 125ps (20% to 80%), unless otherwise noted.)
SUPPLY CURRENT (I
EE
)
vs. TEMPERATURE
MAX9381 toc01
OUTPUT AMPLITUDE (V
OH
- V
OL
)
vs. CLK FREQUENCY
MAX9381 toc02
24
INPUTS AND
OUTPUTS OPEN
SUPPLY CURRENT (mA)
22
800
OUTPUT AMPLITUDE (mV)
-40
-15
10
35
60
85
700
600
20
500
18
400
16
TEMPERATURE (°C)
300
0
0.5
1.0
1.5
2.0
2.5
3.0
CLK FREQUENCY (GHz)
OUTPUT RISE/FALL TIME
vs. TEMPERATURE
MAX9381 toc03
CLK-TO-Q PROPAGATION DELAY
vs. TEMPERATURE
IN-TO-OUT PROPAGATION DELAY (ps)
MAX9381 toc04
125
f
CLK
= 1.5GHz
OUTPUT RISE/FALL TIME (ps)
123
360
350
121
RISE TIME
340
t
PHL
330
t
PLH
119
FALL TIME
117
115
-40
-15
10
35
60
85
TEMPERATURE (°C)
320
-40
-15
10
35
60
85
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Lowest Power 3.0GHz ECL/PECL
Differential Data and Clock D Flip-Flop
Pin Description
PIN
1
2
3
4
5
6
7
8
NAME
D
D
CLK
CLK
V
EE
Q
Q
V
CC
FUNCTION
Noninverting D Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to V
EE
.
Inverting D Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to V
EE
.
Noninverting Clock Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to V
EE
.
Inverting Clock Input to the Flip-Flop. Internally pulled down with a 75kΩ resistor to V
EE
.
Negative Supply
Inverting Q Output from the Flip-Flop. Terminate with a 50Ω resistor to V
CC
- 2V or equivalent.
Noninverting Q Output from the Flip-Flop. Terminate with a 50Ω resistor to V
CC
- 2V or equivalent.
Positive Supply. Bypass from V
CC
to V
EE
with 0.1µF and 0.01µF ceramic capacitors. Place the
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
MAX9381
Detailed Description
The MAX9381 D flip-flop transfers the logic level at the
D input to the Q output on a rising edge transition of the
clock, provided the minimum setup and hold times are
met. By interchanging the CLK and
CLK
inputs, the flip-
flop functions as a falling-edge triggered flip-flop.
The input signals (D,
D
and CLK,
CLK)
are differential
and have a maximum differential input voltage of 3.0V
or V
CC
- V
EE
, whichever is less. To ensure that the out-
puts remain stable when the inputs are left open, each
of the inputs is driven low by a 75kΩ bias resistor con-
nected to V
EE
. If the D and
D
inputs are left open or at
V
EE
, the output is guaranteed to be a differential low on
the next low-to-high transition of the clock. If the CLK
and
CLK
inputs are left open or at V
EE
, the outputs
remain unchanged (Table 1). Terminate the outputs (Q,
Q)
through 50Ω to V
CC
- 2V or an equivalent Thevenin
termination (see the
Output Termination
section).
Table 1. Truth Table*
D,
D
L
H
Open or V
EE
X
CLK,
CLK
↑
↑
↑
Open or V
EE
Q,
Q
L
H
L
No change
*Where
logic states are differential,
↑
is a low-to-high transition
and X signifies a don’t care state.
supply. With V
CC
connected to a positive supply and
V
EE
connected to GND, the outputs are PECL. The out-
puts are ECL when V
CC
is connected to GND and V
EE
is connected to a negative supply.
Applications Information
T Flip-Flop
The MAX9381 can be configured as a T flip-flop by
connecting Q to
D
and
Q
to D. This configuration pro-
vides an output at half the frequency of the clock. The
maximum operating frequency is determined by the
sum of the setup time, the propagation delay of the
ECL/PECL Operation
Output levels are referenced to V
CC
and are consid-
ered PECL or ECL, depending on the level of the V
CC
V
CC
V
ID
V
ID
= 0
V
ILD
(MAX)
V
IHD
(MAX)
V
CC
V
OH
V
OH
- V
OL
V
IHD
(MIN)
V
ID
V
EE
V
ID
= 0
V
ILD
(MIN)
V
OL
V
EE
INPUT VOLTAGE DEFINITION
OUTPUT VOLTAGE DEFINITION
Figure 1. Input and Output Voltage Definitions
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