Low Phase Noise, 1-to-2, 3.3V, 2.5V
LVPECL Output Fanout Buffer
Description
The IDT8SLVP1102I is a high-performance differential LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
IDT8SLVP1102I is characterized to operate from a 3.3V or 2.5V
power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the IDT8SLVP1102I ideal for those clock distribution
applications demanding well-defined performance and repeatability.
One differential input and two low skew outputs are available. The
integrated bias voltage reference enables easy interfacing of
single-ended signals to the device input. The device is optimized for
low power consumption and low additive phase noise.
IDT8SLVP1102I
DATASHEET
Features
•
•
•
•
•
•
•
•
•
•
•
Two low skew, low additive jitter LVPECL output pairs
Differential PCLK, nPCLK pair can accept the following differential
input levels: LVDS, LVPECL, CML
Maximum input clock frequency: 2GHz
Output skew: 5ps (typical)
Propagation delay: 250ps (maximum)
Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
12kHz - 20MHz: 49fs (maximum)
Full 3.3V or 2.5V supply voltage
Maximum device current consumption (I
EE
): 34mA (maximum)
Available in lead-free (RoHS 6), 16-Lead VFQFPN package
-40°C to 85°C ambient operating temperature
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B)
Block Diagram
V
CC
Pin Assignment
V
EE
nc
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
V
EE
1
nc
2
16 15 14 13
12 nQ1
11 Q1
10 nQ0
9 Q0
5
V
CC
nc 3
nc 4
6
PCLK
nc
7
nPCLK
V
REF
Voltage
Reference
IDT8SLVP1102I
16-Lead VFQFPN
3.0mm x 3.0mm x 0.925mm package body
NL Package
Top View
IDT8SLVP1102ANLI MARCH 13, 2018
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©2018 Integrated Device Technology, Inc.
V
REF
nc
8
IDT8SLVP1102I Datasheet
LOW PHASE NOISE, 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 16
2, 3, 4,
13, 14, 15
5
6
7
8
9, 10
11, 12
Name
V
EE
nc
V
CC
PCLK
nPCLK
V
REF
Q0, nQ0
Q1, nQ1
Power
Unused
Power
Input
Input
Output
Output
Output
Pulldown
Pullup/
Pulldown/
Type
Description
Negative supply pins.
Do not connect.
Power supply pin.
Non-inverting differential LVPECL clock/data input.
Inverting differential LVPECL clock/data input. V
CC
/2 default when left
floating.
Bias voltage reference for the PCLK input.
Differential output pair 0. LVPECL interface levels.
Differential output pair 1. LVPECL interface levels.
NOTE:
Pulldown
and
Pullup
refers to an internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
IDT8SLVP1102ANLI MARCH 13, 2018
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©2018 Integrated Device Technology, Inc.
IDT8SLVP1102I Datasheet
LOW PHASE NOISE, 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum
Ratings
may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at
these conditions or any conditions beyond those listed in the
DC
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Input Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model, NOTE 1
ESD - Charged Device Model, NOTE 1
NOTE 1: According to JEDEC/JESD 22-A114/22-C101.
Characteristics or AC Characteristics
is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
product reliability.
Rating
3.63V
-0.5V to V
CC
+ 0.5V
50mA
100mA
±2mA
125°C
-65C to 150C
2000V
1500V
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
Q0 and Q1 terminated
50
to V
CC
– 2V
Test Conditions
Minimum
3.135
Typical
3.3V
Maximum
3.465
34
106
Units
V
mA
mA
Table 3B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
Q0 and Q1 terminated
50
to V
CC
– 2V
Test Conditions
Minimum
2.375
Typical
2.5V
Maximum
2.625
31
103
Units
V
mA
mA
IDT8SLVP1102ANLI MARCH 13, 2018
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©2018 Integrated Device Technology, Inc.
IDT8SLVP1102I Datasheet
LOW PHASE NOISE, 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
Table 3C. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High
Current
Input Low
Current
PCLK, nPCLK
PCLK
nPCLK
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
I
REF
= ±1mA
-10
-150
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 2.0
V
CC
– 1.3
V
CC
– 0.9
V
CC
– 1.65
V
CC
– 1.1
V
CC
– 0.7
V
CC
– 1.5
Minimum
Typical
Maximum
150
Units
μA
μA
μA
V
V
V
Reference Voltage for Input
Bias
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
Table 3D. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REF
V
OH
V
OL
Parameter
Input High
Current
Input Low
Current
PCLK, nPCLK
PCLK
nPCLK
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
I
REF
= ±1mA
-10
-150
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 2.0
V
CC
– 1.3
V
CC
– 0.9
V
CC
– 1.6
V
CC
– 1.1
V
CC
– 0.7
V
CC
– 1.5
Minimum
Typical
Maximum
150
Units
μA
μA
μA
V
V
V
Reference Voltage for Input
Bias
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
IDT8SLVP1102ANLI MARCH 13, 2018
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©2018 Integrated Device Technology, Inc.
IDT8SLVP1102I Datasheet
LOW PHASE NOISE, 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
AC Electrical Characteristics
Table 4. AC Electrical Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
REF
V/t
t
PD
tsk(o)
tsk(p)
tsk(pp)
Parameter
Input Frequency
Input Edge Rate
PCLK,
nPCLK
PCLK,
nPCLK
PCLK, nPCLK to any Qx, nQx
for V
PP
= 0.1V or 0.3V
f
REF
= 100MHz
f
REF
= 122.88MHz Sine Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 122.88MHz Sine Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 122.88MHz Sine Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 1kHz – 40MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 10kHz – 20MHz
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 12kHz – 20MHz
t
R
/ t
F
V
PP
V
CMR
V
O
(pp)
V
DIFF_OUT
Output Rise/ Fall Time
Peak-to-Peak Input Voltage;
NOTE 5, 7
Common Mode Input
Voltage; NOTE 5, 6, 7
Output Voltage Swing,
Peak-to-Peak
Differential Output Voltage
Swing, Peak-to-Peak
V
CC
= 3.3V, f
REF
2GHz
V
CC
= 2.5V, f
REF
2GHz
V
CC
= 3.3V, f
REF
2GHz
V
CC
= 2.5V, f
REF
2GHz
20% to 80%
f
REF
< 1.5GHz
f
REF
> 1.5GHz
35
0.1
0.2
1.0
0.45
0.4
0.9
0.8
0.75
0.65
1.5
1.3
1.5
70
140
5
6
80
157
92
91
38
36
36
60
49
49
110
51
49
49
77
63
63
180
1.5
1.5
V
CC
– 0.6
1.0
1.0
2.0
2.0
250
15
10
230
Test Conditions
Minimum
Typical
Maximum
2
Units
GHz
V/ns
ps
ps
ps
ps
fs
fs
fs
fs
fs
fs
fs
fs
fs
ps
V
V
V
V
V
V
V
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Output Pulse Skew
Part-to-Part Skew; NOTE 3, 4
t
JIT
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 5: V
IL
should not be less than -0.3V. V
IH
should not be higher than V
CC
.
NOTE 6: Common mode input voltage is defined as the crosspoint.
NOTE 7: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to accept
single-ended levels, Figures 1A and 1B.
IDT8SLVP1102ANLI MARCH 13, 2018
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©2018 Integrated Device Technology, Inc.
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