OC-12/STM-4 AND OC-3/STM-1
Clock/Data Recovery Device
894D115I-04
Data Sheet
General Description
The 894D115I-04 is a clock and data recovery circuit. The device
is designed to extract the clock signal from a NRZ-coded STM-4
(OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The
output signals of the device are the recovered clock and retimed
data signals. Input and output are differential signals for best
signal integrity and to support high clock and data rates. All control
inputs and outputs are single-ended signals. An internal PLL is
used for clock generation and recovery. An external clock input is
provided to establish an initial operating frequency of the clock
recovery PLL and to provide a clock reference in the absence of
serial input data. The device supports a signal detect input and a
lock detect output. A bypass circuit is provided to facilitate factory
tests.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Clock recovery for STM-4 (OC-12/STS-12) and
STM-1 (OC-3/STS-3)
Input: NRZ data (622.08 or 155.52 Mbit/s)
Output: clock signal (622.08MHz or 155.52MHz) and retimed
data signal at 622.08 or 155.52 Mbit/s
Internal PLL for clock generation and clock recovery
Differential inputs can accept LVPECL levels
Differential LVDS data and clock outputs
Lock reference input and PLL lock output
19.44MHz reference clock input
Full 3.3V supply mode
-40°C to 85°C operating temperature
Available in lead-free (RoHS 6) package
See 894D115I for a clock/data recovery circuit with a TSSOP
EPAD package and LVPECL outputs
See 894D115I-01 for a clock/data recovery circuit with LVPECL
outputs
Block Diagram
CAP
nCAP
Pin Assignment
V
DDA
DATA_IN
nDATA_IN
GND_PLL
LOCK_DET
STS12
REF_CLK
LOCK_REFN
GND
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DDA
GND_PLL
CAP
nCAP
BYPASS
SD
DATA_OUT
nDATA_OUT
CLK_OUT
nCLK_OUT
DATA_IN
Pulldown
nDATA_IN
Pullup/Pulldown
PLL
894D115I-04
DATA_OUT
0
REF_CLK
Pulldown
nDATA_OUT
1
STS12
Pulldown
SD
Pulldown
LOCK_REFN
Pullup
BYPASS
Pulldown
CLK_OUT
nCLK_OUT
LOCK_DET
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision C January 27, 2016
894D115I-04 Data Sheet
Functional Description
The 894D115I-04 is designed to extract the clock from a
NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input
data signals. The output signals are the recovered clock and
retimed data signals. The device contains an integrated PLL for
clock generation and to lock the output clock to the input data
stream. The PLL attempts to lock to the reference clock input
(REF_CLK) in absence of the serial data stream or if it is forced to
by the control inputs LOCK_REFN or SD. The output clock
frequency is controlled by the STS12 input. The output frequency
is 622.08MHz in STM-4/OC-12/STS-12 mode and 155.52MHz in
STM-1/OC-3/STS-3 mode.
The 894D115I-04 will maintain an output (CLK_OUT/ nCLK_OUT)
frequency deviation of less than ±500ppm with respect to the
REF_CLK reference frequency in a loss of signal state (LOS).
During the LOS state, the data outputs (DATA_OUT/
nDATA_OUT) are held at logic low state. An LOS state of the
894D115I-04 is given when BYPASS is set to the logic low state
and either one of the SD or LOCK_REFN inputs are at a logic low
state.
DATA_IN
Pulldown
nDATA_IN
Pullup/Pulldown
This will enable the use of the SD (signal detect) and the
LOCK_REFN (lock-to-reference) inputs to accept loss of signal
status information from electro-optical receivers. Please refer to
Figure 1, “Signal Detect/PLL Bypass Operation Control Diagram”,
for details.
The lock detect output (LOCK_DET) can be used to monitor the
operating state of the clock/data recovery circuit. LOCK_DET is
set to logic low level when the internal oscillator of the PLL and
the reference clock (REF_CLK) deviate from each other by more
than 500ppm, or when the CDR is forced to lock the REF_CLK
input by the LOCK_REFN or SD control input. LOCK_DET is set
to high when the PLL is locked to the input data stream and
indicates valid clock and data output signals.
The BYPASS pin should be set to logic low state in all
applications. BYPASS set to logic high state is used during factory
test. In BYPASS mode (BYPASS and STS12 are at logic high
state), the internal PLL is bypassed and the inverted REF_CLK
input signal is output at CLK_OUT/nCLK_OUT.
DATA_OUT
nDATA_OUT
PLL Clock
(on-chip)
REF_CLK
Pulldown
STS12
Pulldown
BYPASS
Pulldown
0
1
CLK_OUT
nCLK_OUT
LOCK_REFN
Pullup
SD
Pulldown
LOS
(on-chip)
Figure 1. Signal Detect/PLL BYPASS Operation Control Diagram
©2016 Integrated Device Technology, Inc
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Revision C January 27, 2016
894D115I-04 Data Sheet
Table 1. Signal Detect/PLL BYPASS Operation Control Table
Inputs
STS12
1
1
1
1
1
0
0
0
0
0
BYPASS
0
0
0
0
1
0
0
0
0
1
LOCK_REFN
1
1
0
0
X
1
1
0
0
X
SD
1
0
1
0
X
1
0
1
0
X
DATA_OUT
DATA_IN
LOW
LOW
LOW
DATA_IN
DATA_IN
LOW
LOW
LOW
Not Allowed
Outputs
CLK_OUT
PLL Clock
PLL Clock
PLL Clock
PLL Clock
REF_CLK
PLL Clock
PLL Clock
PLL Clock
PLL Clock
Not Allowed
Table 2. Pin Descriptions
Number
1, 20
2
3
4, 19
5
6
7
8
9
10
11,
12
13,
14
15
16
17, 18
Name
V
DDA
DATA_IN
nDATA_IN
GND_PLL
LOCK_DT
STS12
REF_CLK
LOCK_REFN
GND
V
DD
nCLK_OUT,
CLK_OUT
nDATA_OUT,
DATA_OUT
SD
BYPASS
nCAP, CAP
Power
Input
Input
Power
Output
Input
Input
Input
Power
Power
Output
Output
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pullup/
Pulldown
Type
Description
Analog supply pins.
Non-inverting differential signal input.
Inverting differential signal input. V
DD
/2 default when left floating.
Power supply ground.
Lock detect output. See Table 4A. Single-ended LVPECL interface levels.
STM-4 (OC-12, STS-12) or STM-1 (OC-3, STS-3) selection mode. See Table 4B.
LVCMOS/LVTTL interface levels.
Reference clock input of 19.44MHz. LVCMOS/LVTTL interface levels.
Lock to REF_CLK input. See Table 4C. LVCMOS/LVTTL interface levels.
Power supply ground.
Core supply pin.
Differential clock output pair. LVDS interface levels.
Differential clock output pair. LVDS interface levels.
Signal detect input. Typically, SD is driven by the signal detect output of the
electro-optical module. See Table 4D. Single-ended LVPECL interface levels.
PLL bypass mode. See Table 4E. LVCMOS/LVTTL interface levels.
External loop filter (1.0µF ±10%).
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 3,
Pin Characteristics,
for typical values.
©2016 Integrated Device Technology, Inc
3
Revision C January 27, 2016
894D115I-04 Data Sheet
Table 3. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 4A. LOCK_DET Operation Table
Output
Operation
The PLL is not locked to the serial input data stream if any of these three conditions occur:
A. Internal oscillator and REF_CLK input frequency are not within 500ppm of each other.
B. SD input is at logic LOW state.
C. LOCK_REFN is at logic LOW state.
When the PLL is locked to the serial input data stream, the CLK_OUT and DATA_OUT signals are valid.
LOCK_DET
LOW
HIGH
Table 4B. STS12 Mode Configuration Table
Input
STS12
0
1
Operation
STM-1 (OC-3, STS-3) operation. The clock/data recovery circuit attempts to recover the clock from a 155.52 Mbit/s
input data stream. The output clock frequency is 155.52MHz.
STM-4 (OC-12, STS-12) operation. The clock/data recovery circuit attempts to recover the clock from a 622.08 Mbit/s
input data stream. The output clock frequency is 622.08MHz.
Table 4C. LOCK_REFN Mode Configuration Table
Input
LOCK_REFN
0
1
Operation
Lock to reference clock. CLK_OUT/nCLK_OUT output frequency is within ±500ppm of the reference clock
(REF_CLK). DATA_OUT is set to logic LOW state and nDATA_OUT is set to logic HIGH state. (DATA_OUT = L,
nDATA_OUT = H).
Normal operation.
Table 4D. SD Mode Configuration Table
Input
SD
0
1
Operation
Indicates a loss-of-signal (LOS) condition to the device. CLK_OUT/nCLK_OUT output frequency is within ±500ppm
of the reference clock (REF_CLK). DATA_OUT is set to logic LOW state and nDATA_OUT is set to logic HIGH state.
(DATA_OUT = L, nDATA_OUT = H).
Normal operation.
©2016 Integrated Device Technology, Inc
4
Revision C January 27, 2016
894D115I-04 Data Sheet
Table 4E. BYPASS Mode Configuration Table
Input
BYPASS
0
1
Operation
Normal operation.
PLL bypassed (for factory test). The inverted REF_CLK input signal is output at CLK_OUT/nCLK_OUT.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
50mA
100mA
81.3C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T = -40°C to 85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.10
Typical
3.3
3.3
Maximum
3.465
V
DD
112
10
Units
V
V
mA
mA
Table 5B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T = -40°C to 85°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
Units
V
V
©2016 Integrated Device Technology, Inc
5
Revision C January 27, 2016
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