Si844x/5x QSOP
F
O UR
Features
DC
AND
F
IVE
- C
HANNEL
D
IGITAL
I
SOLA TORS
High-speed operation
to 150 Mbps
Up to 1000 V
RMS
isolation
Precise timing (typical)
ns worst case
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
6 ns minimum pulse width
<10
1.6 mA per channel at 1 Mbps
Transient Immunity 25 kV/µs
< 6 mA per channel at 100 Mbps
Wide temperature range
2.70 V Operation:
–40 to 125 °C at 150 Mbps
< 1.4 mA per channel at 1 Mbps
RoHS-compliant packages
< 4 mA per channel at 100 Mbps
QSOP-16
<
High electromagnetic immunity
Applications
Industrial automation systems
Isolated switch mode supplies
Isolated ADC, DAC
Safety Regulatory Approvals
UL 1577 recognized
Up
CSA component notice 5A
approval
to 1000 V
RMS
for 1 minute
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS
devices offering substantial data rate, propagation delay, power, size,
reliability, and external BOM advantages when compared to legacy
isolation technologies. The operating parameters of these products
remain stable across wide temperature ranges throughout their
service life. For ease of design, only VDD bypass capacitors are
required.
Data rates up to 150 Mbps are supported, and all devices achieve
worst-case propagation delays of less than 10 ns. These devices are
available in a 16-pin QSOP package.
Rev. 1.2 9/13
N
ot
fo R
r N ec
om
ew
m
D e
e s nd
ig e
ns d
Motor control
Power inverters
Communications systems
No start-up initialization required
Wide Operating Supply Voltage:
2.70–5.5 V
Ultra low power (typical)
5 V Operation:
VDE certification conformity
IEC
60747-5-2
(VDE0884 Part 2)
Ordering Information:
See page 25.
Copyright © 2013 by Silicon Laboratories
Si844x/5x QSOP
2
Si844x/ 5x QS OP
Rev. 1.2
N
ot
fo R
r N ec
om
ew
m
D e
e s nd
ig e
ns d
Si844x/5x QSOP
T
ABLE
Section
OF
C
ONTENTS
Page
N
ot
fo R
r N ec
om
ew
m
D e
e s nd
ig e
ns d
Rev. 1.2
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1. Power Supply Bypass Capacitors (Revision C and Revision D) . . . . . . . . . . . . . . . . 23
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Package Outline: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7. Land Pattern: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8. Top Marking: 16-Pin QSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1. 16-Pin QSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3
Si844x/ 5x QS OP
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Operating Temperature*
Supply Voltage
Symbol
T
A
V
DD1
V
DD2
Test Condition
150 Mbps, 15 pF, 5 V
Min
–40
2.70
2.70
Typ
25
—
—
Max
125
5.5
5.5
Unit
°C
V
V
*Note:
The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels,
and supply voltage.
Table 2. Absolute Maximum Ratings
1
Parameter
Storage Temperature
2
Supply Voltage
Input Voltage
Output Voltage
N
ot
fo R
r N ec
om
ew
m
D e
e s nd
ig e
ns d
Symbol
T
STG
T
A
V
I
Min
–65
–40
Typ
—
—
V
DD1
, V
DD2
V
O
I
O
–0.5
—
–0.5
–0.5
—
—
—
—
—
—
—
—
Rev. 1.2
Max
150
125
6.0
V
DD
+ 0.5
V
DD
+ 0.5
10
260
1000
Unit
°C
°C
V
V
V
mA
°C
V
RMS
Ambient Temperature Under Bias
Output Current Drive Channel
Lead Solder Temperature (10 s)
Maximum Isolation (Input to Output) (1 sec)
QSOP-16
Notes:
1.
Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet.
2.
VDE certifies storage temperature from –40 to 150 °C.
4
Si844x/5x QSOP
Table 3. Electrical Characteristics
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Impedance
1
Enable Input High Current
Enable Input Low Current
Si8455Bx
V
DD1
V
DD2
V
DD1
V
DD2
(V
DD1
=5 V±10%, V
DD2
=5 V±10%, T
A
= –40 to 125 °C)
Symbol
V
IH
V
IL
V
OH
V
OL
I
L
Z
O
I
ENH
I
ENL
Test Condition
Min
2.0
—
Typ
—
—
4.8
0.2
—
85
2.0
2.0
Max
—
0.8
—
0.4
±10
—
—
—
Unit
V
V
V
V
µA
µA
µA
loh = –4 mA
lol = 4 mA
V
DD1
,V
DD2
– 0.4
—
—
—
—
—
N
ot
fo R
r N ec
om
ew
m
D e
e s nd
ig e
ns d
V
ENx
= V
IH
V
ENx
= V
IL
DC Supply Current
(All inputs 0 V or at Supply)
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
—
—
—
—
1.6
2.9
7.0
3.1
2.3
2.3
4.5
4.5
—
—
—
—
4.3
3.5
3.6
3.6
—
—
—
—
4.3
4.8
4.2
4.2
Rev. 1.2
2.4
4.4
10.5
4.7
3.5
3.5
6.8
6.8
mA
Si8442Bx
V
DD1
V
DD2
V
DD1
V
DD2
mA
1 Mbps Supply Current
(All inputs = 500 kHz square wave, CI = 15 pF on all outputs)
6.5
5.3
5.4
5.4
mA
Si8455Bx
V
DD1
V
DD2
Si8442Bx
V
DD1
V
DD2
mA
10 Mbps Supply Current
(All inputs = 5 MHz square wave, CI = 15 pF on all outputs)
6.5
6.7
5.9
5.9
mA
Si8455Bx
V
DD1
V
DD2
Si8442Bx
V
DD1
V
DD2
mA
Notes:
1.
The nominal output impedance of an isolator driver channel is approximately 85
,
±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2.
t
PSK(P-P)
is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3.
Start-up time is the time period from the application of power to valid data at the output.
5
京公网安备 11010802033920号
EEWORLD
