71V25761S200PFG datasheet, PDF

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71V25761S200PFG: Descriptionsram 128kx36 sync 3.3V pipelined burst sram; Categorysemiconductor Other integrated circuit (IC); File Size327KB，21 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/; Environmental Compliance

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71V25761S200PFG Overview

sram 128kx36 sync 3.3V pipelined burst sram

71V25761S200PFG Parametric

Parameter Name	Attribute value
Manufacture	IDT (Integrated Device Technology)
Product Category	SRAM
RoHS	Yes
Package / Case	TQFP-100
Packaging	Tube
Factory Pack Quantity	72

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128K X 36

IDT71V25761YS/S

3.3V Synchronous SRAMs

2.5V I/O, Pipelined Outputs,

Burst Counter, Single Cycle Deselect

◆

Features

128K x 36 memory configuration

Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

Commercial and Industrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

Compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array

Description

The IDT71V25761 are high-speed SRAMs organized as 128K x 36.

The IDT71V25761 SRAMs contain write, data, address and control

registers. Internal logic allows the SRAM to generate a self-timed write

based upon a decision which can be left until the end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V25761 can provide four cycles of data for

a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the

LBO

input pin.

The IDT71V25761 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and 165 fine pitch ball grid array (fBGA).

◆

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5297 tbl 01

MAY 2010

DSC-5297/05

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