Data Sheet
FEATURES
Continuous output current
ADP2119: 2 A
ADP2120: 1.25 A
145 mΩ and 70 mΩ integrated MOSFETs
Input voltage range from 2.3 V to 5.5 V
Output voltage from 0.6 V to V
IN
±1.5% output accuracy
1.2 MHz fixed switching frequency
Synchronizable between 1 MHz and 2 MHz
Selectable PWM or PFM mode operation
Current mode architecture
Precision threshold enable input
Power-good flag
Voltage tracking
Integrated soft start
Internal compensation
Startup with precharged output
UVLO, OVP, OCP, and thermal shutdown
10-lead, 3 mm × 3 mm LFCSP_WD package
Supported by
ADIsimPower™
design tool
2 A/1.25 A, 1.2 MHz, Synchronous,
Step-Down DC-to-DC Regulators
ADP2119/ADP2120
TYPICAL APPLICATION CIRCUIT
C1
0.1µF
V
IN
5V
C
IN
22µF
X5R
6.3V
R1
10Ω
ADP2119/ADP2120
1
VIN
PVIN
SW
PGND
GND
EN
10
SYNC/MODE
9
PGOOD
8
TRK
7
FB
6
08716-001
2
V
OUT
3.3V
C
OUT
22µF
X5R
6.3V
R
BOT
2.21kΩ
L
1.5µH
R
TOP
10kΩ
3
R2
10kΩ
4
5
Figure 1.
APPLICATIONS
Point of load conversion
Communications and networking equipment
Industrial and instrumentation
Consumer electronics
Medical applications
GENERAL DESCRIPTION
The ADP2119/ADP2120 are low quiescent current, synchronous,
step-down dc-to-dc regulators in a compact 3 mm × 3 mm
LFCSP_WD package. Both devices use a current mode, constant
frequency pulse-width modulation (PWM) control scheme for
excellent stability and transient response. Under light load conditions,
they can be configured to operate in a pulse frequency modulation
(PFM) mode, which reduces switching frequency to save power.
The ADP2119/ADP2120 support input voltages from 2.3 V to
5.5 V. The output voltage can be adjusted from 0.6 V up to the
input voltage (V
IN
) for the adjustable version, whereas the fixed
output version is available in preset output voltage options of 3.3 V,
2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V. The ADP2119/ADP2120 require
minimal external parts and provide a high efficiency solution with
their integrated power switches, synchronous rectifiers, and internal
compensation. Each IC draws less than 2 µA current from the input
source when it is disabled. Other key features include undervoltage
lockout (UVLO), integrated soft start to limit inrush current at
startup, overvoltage protection (OVP), overcurrent protection
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.
(OCP), and thermal shutdown (TSD).
100
V
IN
= 5V
90 V
OUT
= 1.8V
80
70
EFFICIENCY (%)
PFM
60
50
40
FPWM
30
20
10
08716-002
0
0.01
0.1
OUTPUT CURRENT (A)
1
Figure 2. ADP2119 Efficiency vs. Output Current
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
ADP2119/ADP2120
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Boundary Condition .................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Functional Block Diagram ............................................................ 15
Theory of Operation ...................................................................... 16
Control Scheme .......................................................................... 16
PWM Mode Operation .............................................................. 16
PFM Mode Operation................................................................ 16
Slope Compensation .................................................................. 16
Enable/Shutdown ....................................................................... 16
Data Sheet
Integrated Soft Start ................................................................... 16
Tracking ....................................................................................... 17
Oscillator and Synchronization ................................................ 17
Current Limit and Short-Circuit Protection .............................. 17
Overvoltage Protection (OVP) ................................................. 17
Undervoltage Lockout (UVLO) ............................................... 17
Thermal Shutdown .................................................................... 17
Power Good (PGOOD) ............................................................. 17
Applications Information .............................................................. 18
ADIsimPower Design Tool ....................................................... 18
Output Voltage Selection ........................................................... 18
Inductor Selection ...................................................................... 18
Output Capacitor Selection....................................................... 18
Input Capacitor Selection .......................................................... 19
Voltage Tracking ......................................................................... 19
Typical Application Circuits ......................................................... 20
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
8/12—Rev. 0 to Rev. A
Change to Features Section ............................................................. 1
Added ADIsimPower Design Tool Section ................................. 18
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
6/10—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
SPECIFICATIONS
V
IN
= V
PVIN
= 3.3 V, EN = VIN, SYNC/MODE = VIN at T
J
= −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
VIN and PVIN
VIN Voltage Range
PVIN Voltage Range
Quiescent Current
Shutdown Current
VIN Undervoltage Lockout Threshold
OUTPUT CHARACTERISTICS
Load Regulation
1
Load Regulation
2
Line Regulation
1
Line Regulation
2
FB
FB Regulation Voltage
FB Bias Current
SW
High-Side On Resistance
3
Low-Side On Resistance
3
SW Peak Current Limit
SW Maximum Duty Cycle
SW Minimum On Time
4
TRK
TRK Input Voltage Range
TRK-to-FB Offset Voltage
TRK Input Bias Current
FREQUENCY
Oscillator Frequency
SYNC/MODE
Synchronization Range
SYNC Minimum Pulse Width
SYNC Minimum Off Time
SYNC Input High Voltage
SYNC Input Low Voltage
INTEGRATED SOFT START
Soft Start Time
Symbol
V
IN
V
PVIN
I
VIN
I
SHDN
UVLO
Test Conditions/Comments
ADP2119/ADP2120
Min
2.3
2.3
Typ
Max
5.5
5.5
200
900
2
2.3
Unit
V
V
µA
µA
µA
V
V
%/A
%/A
%/V
%/V
No switching, SYNC/MODE = GND
Switching, no load, SYNC/MODE = VIN
V
IN
= V
PVIN
= 5.5 V, EN = GND
V
IN
rising
V
IN
falling
ADP2119, I
O
= 0 A to 2 A
ADP2120, I
O
= 0 A to 1.25 A
ADP2119, I
O
= 1 A
ADP2120, I
O
= 1 A
2
150
680
0.3
2.2
2.1
0.08
0.08
0.05
0.05
V
FB
I
FB
V
IN
= 2.3 V to 5.5 V
V
IN
= 2.3 V to 5.5 V
V
IN
= V
PVIN
= 3.3 V, I
SW
= 200 mA
V
IN
= V
PVIN
= 3.3 V, I
SW
= 200 mA
High-side switch, V
IN
= V
PVIN
= 3.3 V (ADP2119)
High-side switch, V
IN
= V
PVIN
= 3.3 V (ADP2120)
V
IN
= V
PVIN
= 5.5 V, full frequency
V
IN
= V
PVIN
= 5.5 V, full frequency
0.591
0.6
0.01
145
70
3
2
100
0.609
0.1
190
100
3.5
2.4
100
V
µA
mΩ
mΩ
A
A
%
ns
mV
mV
nA
MHz
MHz
ns
ns
V
V
Clock
cycles
µs
2.5
1.6
TRK = 0 mV to 500 mV
0
−15
600
+15
100
1.2
1.38
2
f
S
1.02
1
100
100
1.3
0.4
All switching frequencies
f
S
= 1.2 MHz
1024
853
105
85
110
2.5
90
2.5
16
0.1
150
150
115
95
PGOOD
Power-Good Range
Power-Good Deglitch Time
PGOOD Leakage Current
PGOOD Output Low Voltage
PGOOD Output Low Resistor
FB rising threshold
FB rising hysteresis
FB falling threshold
FB falling hysteresis
From FB to PGOOD
V
PGOOD
= 5 V
I
PGOOD
= 1 mA
I
PGOOD
= 1 mA
Rev. A | Page 3 of 24
1
200
200
%
%
%
%
Clock
cycles
µA
mV
Ω
ADP2119/ADP2120
Parameter
EN
EN Input Rising Threshold
EN Input Hysteresis
EN Pull-Down Resistor
THERMAL
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
2
Data Sheet
Symbol
Test Conditions/Comments
V
IN
= 2.3 V to 5.5 V
V
IN
= 2.3 V to 5.5 V
Min
1.12
Typ
1.2
100
1
150
25
Max
1.28
Unit
V
mV
MΩ
°C
°C
Specified by the circuit in Figure 54.
Specified by the circuit in Figure 58.
3
Pin-to-pin measurements.
4
Guaranteed by design.
Rev. A | Page 4 of 24
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VIN, PVIN
SW
FB, SYNC/MODE, EN, TRK, PGOOD
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
ADP2119/ADP2120
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
10-Lead LFCSP_WD
θ
JA
40
Unit
°C/W
BOUNDARY CONDITION
θ
JA
is measured using natural convection on a JEDEC 4-layer
board, and the exposed pad is soldered to the printed circuit
board (PCB) with thermal vias.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 5 of 24
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