FQ251 · FQ241 · FQ231 · FQ221 · FQ211 · FQ201 · FQ621· FQ421
FlexQ
TM
I
5 Volt Synchronous x9 First-In/First-Out Queue
Memory Configuration
8,192 x 9
4,096 x 9
2,048 x 9
1,024 x 9
Device
FQ251
FQ241
FQ231
FQ221
Memory Configuration
512 x 9
256 x 9
128 x 9
64 x 9
Device
FQ211
FQ201
FQ621
FQ421
Key Features:
•
•
•
•
•
•
•
•
•
•
Industry leading First-In/First-Out Queues (up to 100MHz)
Independent Write and Read cycle time
5V power supply
Full, Empty, Almost Full, and Almost Empty flag indicators
Preset for Almost Full ( PRAF ) and Almost Empty ( PRAE ) offset values
Programmable PRAF and PRAE offset values
Asynchronous output enable tri-state data output drivers
Available packages: 32 - pin Plastic Lead Chip Carrier (PLCC), 32 - pin Plastic Thin Quad Flat Package
(TQFP)
(0
°
C to 70
°
C) Commercial operating temperature available for cycle time of 10ns and above
(-40
°
C to 85
°
C) Industrial operating temperature available for cycle time of 10ns and above
Product Description:
HBA’s FlexQ™ I offers industry leading FIFO queuing bandwidth (up to 1 Gbps) with a wide range of memory configurations
(from 64 x 9 to 8,192 x 9). System designer has full flexibility of implementing deeper and wider queues using the depth and
width expansion features. Full and Empty indicators allow easy handshaking between transmitters and receivers. User
programmable Almost Full and Almost Empty (Parallel) indicators allow implementation of virtual queue depths.
Asynchronous Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-
matching capability.
These FlexQ™ I devices have low power consumption, hence minimizing system power requirements. In addition, industry
standard 32 - pin PLCC and 32 - pin TQFP are offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, network switching, etc.
5F109C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2003
Page 1 of 26
FQ251 · FQ241 · FQ231 · FQ221 · FQ211 · FQ201 · FQ621· FQ421
FlexQ
TM
I
Block Diagram of Single Synchronous Queue
8,192 x 9 / 4,096 x 9 / 2,048 x 9 / 1,024 x 9 / 512 x 9 / 256 x 9 / 128 x 9 / 64 x 9
RESET (
RST
)
WRITE CLOCK (WCLK)
WRITE ENABLE 1 ( WEN1)
WRITE ENABLE 2/LOAD
( WEN2/ LOAD )
DATA IN (D
8 - 0
)
FULL ( FULL )
ALMOST-FULL (
PRAF
)
FQ251
FQ241
FQ231
FQ221
FQ211
FQ201
FQ621
FQ421
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
READ ENABLE 2 (
REN 2
)
DATA OUT (Q
8 - 0
)
EMPTY ( EMPTY )
ALMOST-EMPTY (
PRAE
)
OUTPUT ENABLE ( OE )
Figure 1. Single Device Configuration Signal Flow Diagram
5F109C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2003
Page 2 of 26
FQ251 · FQ241 · FQ231 · FQ221 · FQ211 · FQ201 · FQ621· FQ421
FlexQ
TM
I
WCLK WEN1 WEN2/
LOAD
LOAD
Write Control
Logic
EMPTY
PRAE
Offset Register
Flag Logic
PRAF
FULL
Write Pointer
D
8-0
Input Register
SRAM
Output Register
Output
Buffer
Q
8-0
OE
Read Pointer
Read Control
Logic
Reset
RST
RCLK REN1 REN 2
Figure 2. Device Architecture
5F109C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2003
Page 3 of 26
FQ251 · FQ241 · FQ231 · FQ221 · FQ211 · FQ201 · FQ621· FQ421
FlexQ
TM
I
D2
D3
D4
D5
D6
D7
31
Ind e x
4
3
2
1
32
30
D1
D0
PRAF
PRAE
GN D
R EN1
RCLK
REN 2
OE
D8
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
28
27
26
25
24
23
22
21
R ST
W E N1
W CLK
W E N 2/ L O A D
V cc
Q8
Q7
Q6
Q5
EMPTY
Q1
Q0
Q2
PL C C - 3 2 (D rw N o : J -0 1 A ;
O rde r c o de : J )
T o p V ie w
FULL
Q3
Q4
26
25
24
23
22
21
20
19
18
17
Ind e x
32
31
30
29
28
27
D1
D0
PRAF
P R AE
RST
D2
D3
D4
D5
D6
D7
D8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
W E N1
W CLK
W E N 2/L O A D
V cc
Q8
Q7
Q6
Q5
GN D
R E N1
RCLK
REN 2
OE
EMPTY
Q0
Q1
Q2
FULL
Q3
T Q FP - 3 2 (D rw N o : PF-0 4 A ;
O rde r c o de : PF)
T o p V ie w
Figure 3. Device Pin-Out
Q4
5F109C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2003
Page 4 of 26
FQ251 · FQ241 · FQ231 · FQ221 · FQ211 · FQ201 · FQ621· FQ421
FlexQ
TM
I
Pin #
TQFP
25
Pin #
PLCC
29
Symbol
Name
Input/Output
Description
Reset is required to initialize Write and Read pointers to
the first position of the queue by setting RST low.
FULL
and PRAF will go high; EMPTY and PRAE
will go low.
Writes data into queue during low to high transitions of
WCLK if WEN1 is activated.
Use as first or as only write enable control for the queue
depending on the state of WEN2/
LOAD
during reset.
During reset, setting WEN2/
LOAD
high places the queue
into the dual write enable mode. WEN1 must be set low
and WEN2/
LOAD
must be set high to perform a valid
write in this mode.
During reset, setting WEN2/
LOAD
low places the queue
into the single write enable/programmable flag mode.
WEN1 must be set low and WEN2/
LOAD
must be set
high to perform a valid write in this mode. In this mode,
WEN1 and WEN2/
LOAD
must be set low to program
the offset values for PRAF and PRAE .
9 - bit wide input data bus.
Reads data from queue during low to high transitions of
RCLK if REN1 and REN 2 are set to low.
Reads data from queue during low to high transitions of
RCLK if REN1 and REN 2 are both set to low.
Reads data from queue during low to high transitions of
RCLK if REN1 and REN 2 are both set to low.
Setting
OE
low activates the data output drivers. Setting
OE
high deactivates the data output drivers (High-Z).
9 - bit wide output data bus.
Queue is full when
FULL
goes low during the low to
high transition of WCLK. This prohibits further writes
into the queue.
Queue is empty when EMPTY goes low during the low
to high transition of RCLK. This prohibits further reads
from the queue.
Queue is almost full when PRAF goes low during the low
to high transition of WCLK. Default (Full-7) or
programmed offset values determine the status of PRAF .
Queue is almost empty when PRAE goes low during the
low to high transition of RCLK. Default (Empty+7) or
programmed offset values determine the status of PRAE .
5V power supply.
0V Ground.
RST
Reset
Input
23
24
27
28
WCLK
WEN1
Write Clock
Write Enable
Input
Input
22
26
WEN2/
LOAD
Write Enable 2 /
Load
Input
26,27,28,
29,30,31
32,01,02
7
6
8
9
20,19,18
17,16,15,
14,13,12
11
30,31,32,
01,02,03,
04,05,06
11
10
12
13
24,23,22,
21,20,19,
18,17,16
15
D
8 - 0
RCLK
REN1
REN 2
OE
Data Inputs
Read Clock
Read Enable 1
Read Enable 2
Output Enable
Input
Input
Input
Input
Input
Q
8 - 0
Data Output
Output
FULL
Full Flag
Output
10
14
EMPTY
Empty Flag
Programmable
Almost-Full
Flag
Programmable
Almost-Empty
Flag
Power
Ground
Output
3
7
PRAF
Output
4
21
5
8
25
9
PRAE
Vcc
GND
Output
N/A
N/A
Table 1. Pin Descriptions
5F109C
© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice.
MARCH 2003
Page 5 of 26
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