1M
×
36-Bit Dynamic RAM Module
(2M
×
18-Bit Dynamic RAM Module)
HYM 361120/40S/GS-60/-70
Advanced Information
•
1 048 576 words by 36-bit organization
(alternative 2 097 152 words by 18-bit)
Fast access and cycle time
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
Fast page mode capability with
40 ns cycle time (-60 version)
45 ns cycle time (-70 version)
Single + 5 V (± 10 %) supply
Low power dissipation
max. 6820 mW active (-60 version)
max. 6160 mW active (-70 version)
CMOS – 66 mW standby
TTL
– 132 mW standby
CAS-before-RAS refresh, RAS-only-refresh,
Hidden refresh
•
12 decoupling capacitors mounted on
substrate
All inputs, outputs and clock fully TTL
compatible
72 pin Single in-Line Memory Module
Utilizes four 1M
×
1-DRAMs and eight
1M
×
4-DRAMs in 300 mil SOJ packages
1024 refresh cycles/16 ms
Tin-Lead contact pads (S - version)
Gold contact pads (GS - version)
HYM 321140S: single sided module with
31.75 mm (1250 mil) height
HYM 321120S: double sided module with
25.40 mm (1000 mil) height
•
•
•
•
•
•
•
•
•
•
•
•
•
Ordering Information
Type
HYM 361140S-60
HYM 361140S-70
HYM 361120S-60
HYM 361120S-70
HYM 361140GS-60
HYM 361140GS-70
HYM 361120GS-60
HYM 361120GS-70
Ordering Code
Q67100-Q959
Q67100-Q958
Q67100-Q942
Q67100-Q741
Q67100-Q1019
Q67100-Q651
Q67100-Q961
Q67100-Q960
Package
L-SIM-72-8
L-SIM-72-8
L-SIM-72-3
L-SIM-72-3
L-SIM-72-8
L-SIM-72-8
L-SIM-72-3
L-SIM-72-3
Descriptions
DRAM module (access time 60 ns)
DRAM module (access time 70 ns)
DRAM module (access time 60 ns)
DRAM module (access time 70 ns)
DRAM module (access time 60 ns)
DRAM module (access time 70 ns)
DRAM module (access time 60 ns)
DRAM module (access time 70 ns)
Semiconductor Group
591
06.94
HYM 361120/40S/GS-60/-70
1M
×
36-Bit
The HYM 361120/40S/GS-60/-70 is a 4 MByte DRAM module organized as 1 048 576 words by
36-bit in a 72-pin single-in-line package comprising four HYB 511000BJ 1M
×
1 DRAMs and eight
HYB 514400BJ 1M
×
4 DRAMs in 300 mil wide SOJ-packages mounted together with twelve
0.2
µF
ceramic decoupling capacitors on a PC board.
The HYM 361120/40S/GS-60/-70 can also be used as a 2 097 152 words by 18-bits dynamic RAM
module by means of connecting DQ0 and DQ18, DQ1 and DQ19, DQ2 and DQ20, …, DQ17 and
DQ35, respectively.
Each HYB 511000BJ and HYB 514400BJ is described in the data sheet and is fully electrically
tested and processed according to Siemens standard quality procedure prior to module assembly.
After assembly onto the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 361120/40S/GS-60/-70 dictates the use of early write cycles.
Pin Definitions and Functions
Pin No.
A0-A9
DQ0-DQ35
CAS0 - CAS3
RAS0, RAS2
WE
Function
Address Inputs
Data Input/Output
Column Address Strobe
Row Address Strobe
Read/Write Input
Power (+ 5 V)
Ground
Presence Detect Pin
No Connection
V
CC
V
SS
PD
N.C.
Presence Detect Pins
-60
PD0
PD1
PD2
PD3
-70
V
SS
V
SS
N.C.
N.C.
V
SS
V
SS
V
SS
N.C.
Semiconductor Group
592
HYM 361120/40S/GS-60/-70
1M
×
36-Bit
Pin Configuration
(top view)
Semiconductor Group
593
HYM 361120/40S/GS-60/-70
1M
×
36-Bit
Block Diagram
Semiconductor Group
594
HYM 361120/40S/GS-60/-70
1M
×
36-Bit
Absolute Maximum Ratings
Operating temperature range ......................................................................................... 0 to + 70 ˚C
Storage temperature range...................................................................................... – 55 to + 125 ˚C
Soldering temperature ............................................................................................................ 260 ˚C
Soldering time ............................................................................................................................. 10 s
Input/output voltage ........................................................................................................ – 1 to + 7 V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation................................................................................................................... 8.68 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
1)
T
A
= 0 to 70 ˚C;
V
CC
= 5 V
±
10 %
Parameter
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 5 mA)
Output low voltage (
I
OUT
= 4.2 mA)
Input leakage current
(0 V <
V
IN
< 6.5 V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V <
V
OUT
< 5.5 V)
Average
V
CC
supply current:
-60 version
-70 version
(RAS, CAS, address cycling,
t
RC
=
t
RC
min.)
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
Symbol
Limit Values
min.
max.
5.5
0.8
–
0.4
20
10
V
V
V
V
µA
µA
2.4
– 1.0
2.4
–
– 20
– 10
Unit
Test
Condition
–
–
–
–
–
–
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
–
–
1240
1120
mA
mA
2), 3)
I
CC2
–
24
mA
–
Average
V
CC
supply current during RAS
I
CC3
only refresh cycles:
-60 version
-70 version
(RAS cycling, CAS =
V
IH
, t
RC
=
t
RC
min.)
2)
–
–
1240
1120
mA
mA
Semiconductor Group
595
京公网安备 11010802033920号
EEWORLD
