KP110
Absolute Pressure Sensor IC
Programmable Temperature Compensation and Calibration
On-Chip Signal Conditioning
Low Cost Bare Die Version
Data Sheet
357
Features
• Ratiometric analog output
• Programmable transfer function performed
by customer
• High accuracy over a large temperature range
up to ± 1.2 kPa (10 ... 85 °C)
• CMOS compatible surface micromachining
• Bare die
KP110
• Specific transfer functions programmable
• Broken wire detection
Type
KP110
Ordering Code
Q62705-K432
Minimum Order Quantity
1 Wafer
Product Description
The KP110 is a miniaturized absolute pressure sensor IC based on the capacitive
principle. It is surface micromachined with a monolithic integrated signal conditioning
circuit realized in the state-of-the-art 0.8 µm BiCMOS technology. As the KP110 is a high
precision IC for cost critical solutions. High accuracy and high sensitivity enable the
dedication in automotive applications as well as consumer products.
In the automotive field the manifold air pressure (MAP) and barometric air pressure
(BAP) are important parameters to compute the air-fuel ratio provided to the engine and
for controlling spark advance to optimize engine efficiency.
Data Book
1
2003-05
KP110
Pad Configuration
(top view of die)
Figure 1
Pad Definitions and Functions
Pad No.
1
2
3
4
5
6
7
Symbol
SERIAL_CLK/
PROG_VOLT
DTA_IN
DTA_OUT
Function
External clock for communication/
Programming voltage
Serial in
Serial out
Supply voltage
Alternative ground pad
Analog pressure signal output
0 V circuit ground potential
V
CC
(GND)
V
OUT
GND
The pads described in the shaded rows of the table above are used during calibration only.
Data Book
2
2003-05
KP110
Die Data
•
•
•
•
•
•
•
•
Semiconductor material: Silicon
Surface passivation: Silicon-Nitride
Die thickness: 675 µm
Die dimension: 4.30 mm x 3.34 mm
Pad metallisation: AlSiCu
Size of the bondpads (area free of passivation): 200 x 200 µm
Rear side metallisation of the chips: no used
The rear side of the chip is electrical connected with GND-Pad
Figure 2
Functional Block Diagram
Data Book
3
2003-05
KP110
Functional Description
Digital Programming Interface
The KP110 digital interface is a 3 wire interface consisting of Data_In, Data_Out and
Clock. A write cycle needs 13 Clock cycles. With the first 12 rising edges of the Clock the
signal on Data_In is clocked into a shift register. The first 3 bits are interpreted as a
register address, the last 9 as data bits. The address and the data word are starting with
the LSB, respectively. During the falling edges of the first 11 Clock cycles the Data_In
must be low. The falling edge of the 12th Clock cycle enables the write frame, at this time
Data_In must be high. A 13th Clock cycle is needed for internal purposes, the signal at
Data_In is ignored.
Simultaneously to the write cycle, a read cycle at Data_Out is performed. The signal at
Data_Out is structured the same way as at Data_In, i.e. 3 address bits and 9 data bits.
The selected register for reading depends on the content of the TESTREG register.
The first valid bit at Data_Out appears with the 13th rising edge of the Clock of the
previous write frame.
The following figure shows the timing diagram:
Figure 3
Timing Diagram
Data Book
4
2003-05
KP110
The table below shows the internal registers of the KP110. For the shaded registers
PROM cells exist. The PROM cells are used for permanent programming of the
calibration data.
In addition to the registers in the table below a 12 x 9 bit RAM table exists for the
linearization and definition of the analog pressure signal. This RAM table is also
overlayed by PROM cells.
To write a 9 bit word to the RAM table at first the data content must be written into the
MEMDAT register. In a further write cycle the desired word is addressed by the 4 LSBs
of the MEMCTL register.
Register
MEMDAT
MEMCTL
GLOBOFF
FUSE_NR
TESTREG
TGAIN
TOFFL
TOFFQ
MODEREG
Function
Data bit 0 to 9
Selection of register of linearization table
Global offset compensation
Fuse number
Selection of register for read cycle
Temperature gain compensation (linear and square)
Linear temperature offset compensation
Square temperature offset compensation
Selection of registers for programming of PROM
The shaded registers in the table are overlayed with PROM
Nonvolatile Memory
Each PROM cell consists of a thin polysilicon wire located in a small evacuated cavity.
The cells are called HR-fuses. In order to write a logic "1" to a HR-cell the wire has to be
cut with a current pulse. Since the current can reach up to 100 mA only a single HR-fuse
can be programmed at a time.
The desired bit within a HR-fuse register is addressed by a register called FUSE_NR. In
case of the linearization table the desired PROM register itself is addressed by the
MEMCTL-register. In order to program the GLOBOFF, TGAIN, TOFFL and TOFFQ
register the MODREG-register is used for addressing.
After the correct addressing of PROM register and bit a fuse pulse has to be applied to
pad 1. The requirements for the pulse voltage, length and slew rate are given in the
electrical characteristics.
The exact sequences for RAM/PROM reading/writing are available on request.
Data Book
5
2003-05
京公网安备 11010802033920号
EEWORLD
