PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
PIN DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
4Mb, 512K x 8, Asynchronous, Low
Power SRAM Memory Array
AVAILABILITY:
DSCC SMD 5962-95600
QML-Q Compliant
Mil 883 Compliant
FEATURES:
High Speed, Asynchronous operation
Fully Static, No Clocks required
Center Power & Ground for improved noise
immunity
Easy Memory Array expansion with use of Chip
Select (CS\) and Output Enable (OE\)
All Inputs/Outputs are TTL compatible
Low Power with Data Retention Functionality
Product Access Speed Options:
o
15, 17, 20, 25, 35 and 45ns
Package Option:
o
36LD-CSOJ
FUNCTIONAL DESCRIPTION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SIGNAL NAME
A0
A1
A2
A3
A4
CE\
IO 0
IO 1
VCC
VSS
IO 2
IO 3
WE\
A5
A6
A7
A8
A9
PIN
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
SIGNAL NAME
NC
A18
A17
A16
A15
OE\
IO 7
IO 6
VSS
VCC
IO 5
IO 4
A14
A13
A12
A11
A10
NC
FUNCTIONAL BLOCK
DATE CODE
LOT CODE
MTS1512K8CssLSJ2x
INPUT BUFFER
The MTS1512K8C is a high-performance Low Power
CMOS Static Random Access Memory (SRAM),
organized as 512K words by 8-bits wide, containing a
total density of 512K bytes. Memory expansion is easily
achieved through use of the Chip-Select (CS\) and
Output Enable (OE\) control inputs along with the tri-
state output drivers. Writing to the device is
accomplished by driving CS\ and WE\ LOW. Data on
the eight IO pins (IO0-IO7) is then written into the
addressed location specified on the Address Input pins
(A0-A18).
Reading from the MTS1512K8C is accomplished by
driving Chip Select (CS\) and Output Enable (OE\) LOW,
while forcing Write Enable (WE\) HIGH. Under these
stimulus conditions, the contents of the addressed
memory location (A0-A18) will be available on the
Output pins (IO0-IO7).
The MTS1512K8C is placed into an inactive, High-
Impedance state when the device has been de-selected
by driving Chip-Select (CS\) HIGH. The eight Input-
Output lines (IO0-IO7) are also in a High-Impedance
state when the MTS1512K8C is placed into a WRITE
operation by driving Chip-Select (CS\) and Write Enable
(WE\) LOW. This device supports Low Voltage Data
Retention.
MTS1512K8C-L - Rev 1.1 - 07/12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE\
WE\
IO 0
IO 1
ROW DECODE
SENSE AMP
512K x 8
Asynchronous
SRAM
ARRAY
2048 Rows
2048 Columns
IO 2
IO 3
IO 4
IO 5
POWER
DOWN
COLUMN DECODE
IO 6
IO 7
OE\
MAXIMUM RATINGS
PARAMETER
Operating Temperature
Storage Temperature
Supply Voltage Relative to GND
DC Voltage applied to Outputs in
High-Z
DC Input Voltage
SYMBOL
T
A
T
STG
V
S
V
OZG
V
G
LIMIT
-55 to +125
-65 to 150
-0.5 to VCC+0.5
-0.5 to VCC+0.5
-0.5 to VCC+0.5
UNITS
˚C
˚C
V
V
V
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
A11
A12
A13
A14
A15
A16
A17
A18
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Deselect to DR time
Operation Recovery
SYMBOL
V
DR
I
CCDR
t
CDR
t
R
V
CC
= V
DR
= 2.0V, CS\
≥
V
CC
-0.3V, V
IN
≥
V
CC
- 0.3V or V
IN
≤
0.3V
0
t
RC
CONDITIONS
MIN
2
10
MAX
UNITS NOTE(S)
V
mA
ns
ns
4
4,11
AC SWITCHING CHARACTERISTICS
READ
15ns
MTS1512K8C15L
17ns
MTS1512K8C20L
20ns
MTS1512K8C25L
PARAMETER
VCC to First Access
READ Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable Access Time
Output Enable to Output in Low-Z
Output Disable to Ouput in High-Z
Chip Enable to Power-Up
Chip Disable to Power-Down
SYMBOL
t
POWER
t
RC
t
AC
t
ACS
t
OH
t
CLZ
t
CHZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
MIN
100
15
-
-
3
3
0
-
0
-
0
-
MAX
-
-
15
15
-
-
7
7
-
7
-
15
MIN
100
20
-
-
3
3
0
-
0
-
0
-
MAX
-
-
17
17
-
-
8
8
-
8
-
17
MIN
100
25
-
-
3
3
0
-
0
-
0
-
MAX
-
-
20
20
-
-
8
10
-
8
-
20
UNITS NOTE(S)
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,7
4,6,7
4,7
4,6,7
15
25ns
MTS1512K8C25L
35ns
MTS1512K8C35L
45ns
MTS1512K8C45L
PARAMETER
VCC to First Access
READ Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable Access Time
Output Enable to Output in Low-Z
Output Disable to Ouput in High-Z
Chip Enable to Power-Up
Chip Disable to Power-Down
MTS1512K8C-L - Rev 1.1 - 07/12
SYMBOL
t
POWER
t
RC
t
AC
t
ACS
t
OH
t
CLZ
t
CHZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
MIN
100
25
-
-
3
3
0
-
0
-
0
-
MAX
-
-
25
25
-
-
10
12
-
10
-
25
MIN
100
15
-
-
3
3
0
-
0
-
0
-
MAX
-
-
15
15
-
-
12
15
-
12
-
35
MIN
100
20
-
-
3
3
0
-
0
-
0
-
MAX
-
-
20
20
-
-
15
22
-
15
-
45
UNITS NOTE(S)
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,7
4,6,7
4,7
4,6,7
15
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
PRELIMINARY
MTS1512K8CxxLSJ2
4Mb Monolithic SRAM
WRITE
15ns
MTS1512K8C15L
17ns
MTS1512K8C20L
20ns
MTS1512K8C25L
PARAMETER
WRITE Cycle Time
Chip Enable to End of WRITE
Address Setup Time
Address Hold from End of WRITE
Address Valid to End of WRITE
WRITE Pulse Width
Data Setup Time
Data Hold Time
WRITE Disable to Output in Low-Z
WRITE Enable to Output in High-Z
SYMBOL
t
WC
t
CW
t
AS
t
AH
t
AW
t
WP
t
DS
t
DH
t
WLZ
t
WHZ
MIN
15
10
0
0
10
10
8
0
4
-
MAX
-
-
-
-
-
-
-
-
-
7
MIN
17
12
0
0
12
12
9
0
4
-
MAX
-
-
-
-
-
-
-
-
-
8
MIN
20
14
0
0
14
14
10
0
5
-
MAX
-
-
-
-
-
-
-
-
-
8
UNITS NOTE(S)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,6,7
4,6,7
25ns
MTS1512K8C25L
35ns
MTS1512K8C35L
45ns
MTS1512K8C45L
PARAMETER
WRITE Cycle Time
Chip Enable to End of WRITE
Address Setup Time
Address Hold from End of WRITE
Address Valid to End of WRITE
WRITE Pulse Width
Data Setup Time
Data Hold Time
WRITE Disable to Output in Low-Z
WRITE Enable to Output in High-Z
SYMBOL
t
WC
t
CW
t
AS
t
AH
t
AW
t
WP
t
DS
t
DH
t
WLZ
t
WHZ
MIN
25
16
0
0
16
16
10
0
5
MAX
MIN
35
18
0
0
18
18
12
0
5
MAX
MIN
45
24
0
0
24
24
15
0
5
MAX
UNITS NOTE(S)
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,6,7
4,6,7
10
10
12
ns
MTS1512K8C-L - Rev 1.1 - 07/12
Minco Technology Labs, LLC reserves the right to change products or specification without notice.
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