CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the
Output Clamp Voltage, V
OC
.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Quiescent Supply Current, ON
Quiescent Supply Current, OFF
Output Clamping Voltage
Output Clamping Energy
Output Leakage Current
V
DD
= 5V, T
A
= -40
o
C to 125
o
C, Unless Otherwise Specified
SYMBOL
I
DD
I
DD
V
OC
E
OC
I
O LEAK
TEST CONDITIONS
All Outputs ON, 0.5A Load Per Output
All Outputs OFF
I
LOAD
= 0.5A, Output Programmed OFF
I
LOAD
= 0.5A, Output ON
Output Programmed OFF
V
O
= 24V
V
O
= 14V
V
O
= 5V
MIN
-
-
27
20
-
-
-
-
1.05
-
-
1.6
50
-
TYP
5
0.2
32
-
150
150
150
-
1.5
1
2
1.8
80
0
MAX
10
-
40
-
1000
500
200
1
-
10
10
2.0
250
1
UNITS
mA
mA
V
mJ
µA
µA
µA
Ω
A
µs
µs
V
µs
V
Output ON Resistance
Output Current Limit
Turn-On Delay
Turn-Off Delay
Fault Reference Voltage
Fault Reset Delay (After CE Low
to High Transition)
Output OFF Voltage
LOGIC INPUTS
r
DS(ON)
I
O LIMIT
t
PHL
t
PLH
V
OREF
t
UD
V
OFF
I
LOAD
= 0.5A (Note 3)
Output Programmed ON, V
OUT
> 3V
I
O
= 500mA, No Reactive Load
I
O
= 500mA, No Reactive Load
Output Programmed ON, Fault Detected
If V
O
> V
OREF
See Figure 1
Output Programmed OFF, Output Pin
Floating
(MOSI, CE, SCK and RESET)
V
T-
V
T+
V
H
I
I
C
I
(MISO)
V
OL
V
OH
I
OL
= 1.6mA
I
OL
= 0.8mA
-
V
DD
- 1.3V
0.2
V
DD
- 0.2V
0.4
-
V
V
V
DD
= 5V
±
10%
V
DD
= 5V
±
10%
V
T+
- V
T-
V
DD
= 5.5V, 0 < V
I
< V
DD
0 < V
I
< V
DD
0.2V
DD
-
0.85
-10
-
0.3V
DD
0.6V
DD
1.4
-
-
-
0.7V
DD
2.25
+10
20
V
V
V
µA
pF
Threshold Voltage at Falling
Edge
Threshold Voltage at Rising
Edge
Hysteresis Voltage
Input Current
Input Capacitance
LOGIC OUTPUT
Output LOW Voltage
Output HIGH Voltage
2
CA3282
Electrical Specifications
PARAMETER
Output Three State Leakage
Current
Output Capacitance
V
DD
= 5V, T
A
= -40
o
C to 125
o
C, Unless Otherwise Specified
(Continued)
SYMBOL
I
OL
C
OUT
TEST CONDITIONS
V
DD
= 5.25V, 0 < V
O
< V
DD
,
CE Pin Held High
0 < V
O
< V
DD
, CE Pin Held High
-
-
20
pF
MIN
-10
TYP
-
MAX
+10
UNITS
µA
Serial Peripheral Interface Timing
PARAMETER
Operating Frequency
Enable Lead Time
Enable Lag Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Enable Time
Disable Time
Data Valid Time
Output Data Hold Time
Rise Time (MISO Output)
Rise Time SPI Inputs (SCK, MOSI, CE)
Fall Time (MISO Output)
Fall Time SPI Inputs (SCK, MOSI, CE)
NOTES:
(See Figure 1B)
SYMBOL
f
OPER
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(12)
(13)
(13)
t
LEAD
t
LAG
t
wSCK
H
TEST CONDITIONS
MIN
D.C.
-
-
-
-
-
-
-
-
-
0
TYP
Note 4
<100
<100
50
50
20
20
50
150
75
50
35
-
45
-
MAX
3.0
200
200
100
100
50
50
100
300
150
-
100
50
100
50
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
wSCK
L
t
SU
t
H
t
EN
t
DIS
t
V
t
HO
t
rSO
t
rSI
t
fSO
t
fSI
V
DD
= 20% to 70%, C
L
= 200pF
V
DD
= 20% to 70%, C
L
= 200pF
V
DD
= 70% to 20%, C
L
= 200pF
V
DD
= 70% to 20%, C
L
= 200pF
-
-
-
-
3. Refer to Figure 4A for I
OUT
current vs V
SAT
voltage. Typical r
DS(ON)
values are given for -40
o
C, 25
o
C, 105
o
C and 125
o
C temperatures.
4. The Maximum Operating Frequency is typically greater than 10MHz but it is application limited primarily by external SPI input rise/fall
times and MISO output loading.
Timing Diagrams
CE
SCK
(CPOL = 0, CPHA = 1)
MSB
6
5
4
3
2
1
LSB
INTERNAL STROBE FOR DATA CAPTURE
FIGURE 1A. DATA AND CLOCK TIMING DIAGRAM
3
CA3282
Timing Diagrams
CE
(INPUT)
(2)
SCK
(INPUT)
LAST BIT
TRANSMITTED
(5)
(4)
(1)
(13)
(12)
(3)
(Continued)
MISO
(OUTPUT)
HIGH
Z
D70
(8)
(10)
D71
(6)
(7)
D60
(11)
D61
D10
(9)
D11
FAULT-INDUCED
TURN-OFF
MOSI
(INPUT)
DRIVER
OUTPUT
OLD
t
PHL
t
PLH
NEW
t
UD
FIGURE 1B.
SPI TIMING DIAGRAM
RESET
CE
SCK
MOSI
7
6
5
4
3
2
1
0
MISO
7
6
5
4
3
2
1
0
OUTPUTS
OLD
NEW
FAULTS
RESET
FIGURE 2. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET
Signal Descriptions
Power Output Drivers, Output 0 - Output 7
- The input and
output bits corresponding to Output 0 thru Output 7 are
transmitted and received most significant bit (MSB) first via
the SPI bus. The outputs are provided with current limiting
and voltage sense functions for fault indication and protec-
tion. The nominal load current for these outputs is 500mA,
with current limiting set to a minimum of 1.05A. An on-chip
clamp circuit capable of handling 500mA is provided at each
output for clamping inductive loads.
RESET
- Active low reset input. When this input line is low,
the shift register and output latches are configured to turn off
all output drivers. A power on clear function may be imple-
mented by connecting this pin to V
DD
with an external resis-
tor, and to V
SS
with an external capacitor. In any case, this
pin must not be left floating.
CE
- Active low chip enable. Data is transferred from the shift
register to the outputs on the rising edge of this signal. The
falling edge of CE loads the shift register with the output volt-
age sense bits coming from the output stages. The output
driver for the MISO pin is enabled when this pin is low. CE
must be a logic low prior to the first serial clock (SCK) and
must remain low until after the last (eighth) serial clock cycle.
A low level on CE also activates an internal disable circuit
used for unlatching output states that are in a fault mode as
4
CA3282
sensed by an out of saturation condition. A high on CE
forces MISO to a high impedance state. Also, when CE is
high, the octal driver ignores the SCK and MOSI signals.
SCK, MISO, MOSI
- See Serial Peripheral Interface (SPI)
section in this data sheet.
V
DD
and V
SS
(GND)
- Positive and negative power supply
lines.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) utilized by the CA3282
is a serial synchronous bus for control and data transfers.
The Clock (SCK), which is generated by the microcomputer,
is active only during data transfers. In systems using
CDP68HC05 family microcomputers, the inactive clock
polarity is determined by the CPOL bit in the microcom-
puter’s control register. The CPOL bit is used in conjunction
with the clock phase bit, CPHA to produce the desired clock
data relationship between the microcomputer and octal
driver. The CPHA bit in general selects the clock edge which
captures data and allows it to change states. For the
CA3282, the CPOL bit must be set to a logic zero and the
CPHA bit to a logic one. Configured in this manner, MISO
(output) data will appear with every rising edge SCK, and
MOSI (input) data will be latched into the shift register with
every falling edge of SCK. Also, the steady state value of the
inactive serial clock, SCK, will be at a low level. Timing dia-
grams for the serial peripheral interface are shown in Figure 1.
SPI Signal Descriptions
MOSI (Master Out/Slave In)
- Serial data input. Data bytes
are shifted in at this pin, most significant bit (MSB) first. The
data is passed directly to the shift register which in turn con-
trols the latches and output drivers. A logic “0” on this pin will
program the corresponding output to be ON, and a logic “1”
will turn it OFF.
MISO (Master In/Slave Out)
- Serial data output. Data bytes
are shifted out at this pin, most significant bit (MSB) first.
This pin is the serial output from the shift register and is
three stated when CE is high. A high for a data bit on this pin
indicates that the corresponding output is high. A low on this
pin for a data bit indicates that the output is low. Comparing
the serial output bits with the previous input bits, the micro-
computer implements the diagnostic data supplied by the
CA3282.
SCK
- Serial clock input. This signal clocks the shift register
SCK and new MOSI (input) data will be latched into the shift
register on every falling edge of SCK. The SCK phase bit,
CPHA, and polarity bit, CPOL, must be set to 1 and 0,
respectively in the microcomputer’s control register.
Serial Peripheral Interface (SPI) protocol. Each channel is
independently controlled by an output latch and a common
RESET line that disables all eight outputs. Byte timing with
asynchronous reset is shown in Figure 4. The circuit
receives 8-bit serial data by means of the serial input
(MOSI), and stores this data in an internal register to control
the output drivers. The serial output (MISO) provides 8-bit
diagnostic data representing the voltage level at the driver
output. This allows the microcomputer to diagnose the con-
dition at the output drivers. The device is selected when the
chip enable (CE) line is low. When (CE) is high, the device is
deselected and the serial output (MISO) is placed in a three-
state mode. The device shifts serial data on the rising edge
of the serial clock (SCK), and latches data on the falling
edge. On the rising edge of chip enable (CE), new input data
from the shift register is latched in the output drivers. The
falling edge of chip enable (CE) transfers the output drivers
fault information back to the shift register. The output drivers
have low ON voltage at rated current, and are monitored by
a comparator for an out of saturation condition, in which
case the output driver with the fault becomes unlatched and
diagnostic data is sent to the microcomputer via the MISO
line. A typical microcomputer interface circuit is shown in
Figure 2. Also, the CA3282 may be cascaded with another
CA3282 octal driver.
Shift Register
The shift register has both serial and parallel inputs and out-
puts. Serial output and input data are simultaneously trans-
ferred to and from the SPI bus. The parallel outputs are
latched into the output latch in the CA3282 at the end of a
data transfer. The parallel inputs jam diagnostic data into the
shift register at the beginning of a data transfer cycle.
CDP68HC05C4
MICROCOMPUTER
PORT
MOSI
MISO
SCK
RESET
CE
MOSI
MISO
SCK
CA3282
RESET
FIGURE 3. TYPICAL MICROCOMPUTER INTERFACE WITH
THE CA3282
Output Latch
The output latch holds input data from the shift register
which is used to activate the outputs. The latch circuit may
be cleared by a fault condition (to protect the overloaded out-
puts), or by the RESET signal.
Functional Descriptions
The CA3282 is a low operating power, high voltage, high cur-
rent, octal power driver featuring eight channels of open
drain NDMOS output drivers. The drivers have low satura-
tion voltage and output short circuit protection, suited for
driving resistive or inductive loads such as lamps, relays and
solenoids. Data is transmitted to the device serially using the
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