PX-721-EAT-GAAN-45M8240000 datasheet, PDF

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PX-721-EAT-GAAN-45M8240000: DescriptionLVCMOS Output Clock Oscillator, 45.824MHz Nom, ROHS COMPLIANT, HERMETIC SEALED PACKAGE-6; CategoryPassive components oscillator; File Size620KB，9 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

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PX-721-EAT-GAAN-45M8240000 Overview

LVCMOS Output Clock Oscillator, 45.824MHz Nom, ROHS COMPLIANT, HERMETIC SEALED PACKAGE-6

PX-721-EAT-GAAN-45M8240000 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	1262820232
package instruction	ROHS COMPLIANT, HERMETIC SEALED PACKAGE-6
Reach Compliance Code	compliant
Other features	ENABLE/DISABLE FUNCTION; TR, 7 INCH
maximum descent time	1.2 ns
Frequency Adjustment - Mechanical	NO
frequency stability	30%
JESD-609 code	e4
Installation features	SURFACE MOUNT
Nominal operating frequency	45.824 MHz
Maximum operating temperature	70 °C
Minimum operating temperature
Oscillator type	LVCMOS
Output load	15 pF
physical size	7.0mm x 5.0mm x 1.62mm
longest rise time	1.2 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Gold (Au) - with Nickel (Ni) barrier

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PX-721

Single Frequency HPLL XO

PX-721

Descrip on

The PX-721 is a crystal oscillator, XO, based upon Vectron’s HPLL high performance phase locked loop frequency mul plier ASIC, that combines

key digital synthesis techniques with VI’s proven core analog technology blocks. A standard low frequency crystal provides the reference to

the frac onal-n synthesizer so that virtually any frequency between 10MHz and 1200 MHz can be factory programmed allowing quick turn

manufacturing.

Features

Applica ons

Features

• Industry Standard Package, 5.0 x 7.0 x 1.8 mm

• HPLL High Performance PLL ASIC

• Ji er < 500 fs-rms (12 kHz to 20 MHz)

• Output Frequencies from 10 MHz to 1200 MHz

• Spurious Suppression, 70 dBc Typical

• 2.5V or 3.3V Supply Voltage

• LVCMOS, LVPECL or LVDS Output Conﬁgura ons

• Output Enable

• Compliant to EC RoHS Direc ve

Applica ons

PLL circuits for clock smoothing and frequency transla on

Descrip on

Standard

• 1-2-4 Gigabit Fibre Channel

• 10 Gigabit Fibre Channel

• 10GbE LAN / WAN

• Synchronous Ethernet

• OC-192

• SONET / SDH

INCITS 352-2002

INCITS 364-2003

IEEE 802.3ae

ITU-T G.8262

ITU-T G.709

GR-253-CORE Issue4

Block Diagram

COutput

Output

XTAL

LVCMOS

LVPECL

LVDS

HPLL

OE or NC

Gnd

Figure 1 - Block Diagram

Page 1 of 9

Vectron Interna onal • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • h p://www.vectron.com

Rev2: 14 November 2012

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