TELEFUNKEN Semiconductors
U4286BM
AM / FM-PLL
Description
The U4286BM is an integrated circuit in BICMOS
technology for frequency synthesizer. It performs all the
functions of a PLL radio tuning system and is controlled
by I
2
C bus. The device is designed for all frequency
synthesizer applications of radio receivers, as well as
RDS (
Radio Data System
) applications.
Features
D
Reference oscillator up to 15 MHz
D
Two programmable 16 bit dividers
adjustable from 2 to 65535
D
Two programmable switching outputs (open drain up
to 20 V)
D
Fine tuning steps: AM
y
1 kHz
FM
y
2 kHz
D
Few external component requirements due to
integrated loop-transistor for AM/FM
D
High signal/ noise ratio
Block Diagram
SWO 1
OSCIN
OSCOUT
14
Oscillator
15
2
3
4
7
Latch
I
2
C–BUS
Interface
Shift register
SWO 2
6
5
R–Divider
Switching outputs
Latch
Status
11
Phase
detector
Preamplifier
SCL
SDA
AS
FMOSC
Latch
Current
sources
:2
PDFM
PDAM
PDFMO
PDAMO
12
10
AMOSC
9
Preamplifier
AM/FM
switch
8
GND 2
N–Divider
1
VDD
Figure 1.
Analogue
outputs 13
16
GND 1
93 7581 e
Rev. A1: 19.08.1996
Preliminary Information
1 (9)
U4286BM
Pin Description
V
DD
SCL
1
2
3
4
16
15
14
13
GND
OSCOUT
OSCIN
PDAMO
PDAM
PDFM
PDFMO
AMOSC
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TELEFUNKEN Semiconductors
SDA
AS
SWO 1
SWO 2
FMOSC
GND 2
U 4286 BM
5
6
7
8
94 7908 e
12
11
10
9
Symbol
V
DD
SCL
SDA
AS
SWO 1
SWO 2
FMOSC
GND 2
AMOSC
PDFMO
PDFM
PDAM
PDAMO
OSCIN
OSCOUT
GND 1
Function
Supply voltage
I
2
C bus clock
I
2
C bus data
Address selection
Switching output 1
Switching output 2
FM oscillator input
Ground 2 (analog)
AM oscillator input
FM analogue output
FM current output
AM current output
AM analogue output
Oscillator input
Oscillator output
Ground 1 (digital)
Functional Description
The U4286BM is controlled via the 2-wire I
2
C bus. For
programming there are one module address byte, two
subaddress bytes and five data bytes.
The module address contains a programmable address bit
A 1 which with address select input AS (Pin 4) makes it
possible to operate two U4286BM-B in one system. If bit
A 1 is identical with the status of the address select input
AS, the chip is selected .
The subaddress determines which one of the data bytes is
transmitted first. If subaddress of R - divider is
transmitted, the sequence of the next data bytes is DB 0
(Status), DB 1 and DB 2.
If subaddress of N - divider is transmitted, the sequence
of the next data bytes is DB 3 and DB 4. The bit
organisation of the module address, subaddress and 5 data
bytes are shown in figure 2.
Each transmission on the I
2
C bus begins with the
“START”- condition and has to be ended by the “STOP”-
condition (see figure 3).
The integrated circuit U4286BM has two separate inputs
for AM and FM oscillator. Pre-amplified AM signal is
directed to the 16 bit N-divider via AM/ FM switch,
whereas (pre-amplified) FM signal is first divided by a
fixed prescaler ( :2 ). AM/ FM switch is controlled by
software. Tuning steps can be selected by 16 bit
R-divider. Further there is a digital memory phase
detector. There are two separate current sources for AM
and FM amplifier (charge pump) as given in electrical
characteristics. It allows independent adjustment of gain,
whereby providing high current for high speed tuning and
low current for stable tuning.
2 (9)
Preliminary Information
Rev. A1: 19.08.1996
U4286BM
Transmission protocol
S
MSB
Address
A7
LSB
A
A0
Subaddress
R-divider
A
Data 0
A
TELEFUNKEN Semiconductors
Data 1
A
Data 2
A
P
MSB
S
A7
Address
LSB
A
A0
Subaddress
N-divider
A
Data 3
A
Data 4
A
A
P
S = Start
P = Stop
A = Acknowledge
Figure 3.
Absolute Maximum Ratings
Parameters
Supply voltage
Pin 1
Input voltage
Pin 2, 3, 4, 7, 9, 14, 15
Output current
Pin 3, 5, 6
Output drain voltage
Pin 5, 6
Output voltage
Pin 10, 13
Output current
Pin 10, 13
Ambient temperature range
Storage temperature range
Junction temperature
Electrostatic handling (MIL Standard 883C)
Symbol
V
DD
V
I
I
O
V
OD
V
AO
I
AO
T
amb
T
stg
T
j
ESD
"
V
Value
–0 to +6
–0.3 to V
DD
+ 0.3
–1 to +5
20
15
–1 to +20
–25 to +85
–40 to +125
125
2000
Unit
V
V
mA
V
V
mA
_
C
_
C
_
C
V
Thermal Resistance
Parameters
Junction ambient
Symbol
R
thJA
Value
160
Unit
K/W
4 (9)
Preliminary Information
Rev. A1: 19.08.1996
TELEFUNKEN Semiconductors
U4286BM
Symbol
V
DD
I
DD
V
SFM
V
SFM
V
SAM
V
SOSC
25
50
25
100
Min.
4.5
Typ.
5.0
6.0
Max.
5.5
11.6
Unit
V
mA
mV
mV
mV
mV
Electrical Characteristics
V
DD
= 5 V, T
amb
= 25°C, unless otherwise specified
Parameters
Test Conditions / Pins
Supply voltage
Pin 1
Quiescent
Pin 1
supply current
FM Input Sensitivity, R
G
= 50
W
FMOSC
f
i
= 70 to 120 MHz
Pin 7
f
i
= 120 to 130 MHz
Pin 7
AM Input Sensitivity, R
G
= 50
W
AMOSC
f
i
= 0.5 to 35 MHz
Pin 9
Oscillator Input Sensitivity, R
G
= 50
W
OSCIN
f
i
= 0.1 to 15 MHz
Pin 14
Switching Output SWO 1, SWO 2 (Open Drain)
Output voltage
Pin 5, 6
LOW
I
L
= 1 mA
I
L
= 0.1 mA
LOW
Pin 5, 6
Output leakage current
V5, V6 = 20 V
HIGH
Phase Detector PDFM
Output current 1
Pin 11
Output current 2
Pin 11
Phase Detector PDAM
Output current 1
Output current 2
Analogue Output PDFMO, PDAMO
Saturation voltage
I = 15 mA
Leakage current
I
2
C Bus SCL, SDA, AS
Input voltage
HIGH
LOW
Output voltage
Acknowledge LOW
Clock frequency
Rise time SDA, SCL
Fall time SDA, SCL
Period of SCL
HIGH
LOW
Pin 10, 13
Pin 10, 13
Pin 2, 3, 4
V
sat
I
LEAK
V
iBUS
3.0
0
I
SDA
= 3 mA
Pin 3
Pin 2
Pin 2, 3
Pin 2, 3
Pin 2
V
O
f
SCL
t
r
t
f
t
H
t
L
4.0
4.7
0.4
100
1
300
V
kHz
m
s
ns
V
DD
1.5
V
SWOL
V
SWOL
I
OHL
200
20
400
100
100
mV
mV
nA
Pin 12
Pin 12
"
I
"
I
"
I
"
I
PDFM
PDFM
400
100
75
20
500
125
100
25
600
150
125
30
m
A
m
A
m
A
m
A
mV
m
A
PDAM
PDAM
270
400
1
V
V
m
s
m
s
Rev. A1: 19.08.1996
Preliminary Information
5 (9)
FPGA/CPLD
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