U6084B
PWM Power Control with Automatic Duty Cycle Reduction
Description
The U6084B is a bipolar technology PWM-IC designed
for the control of an N-channel power MOSFET used as
a high-side switch. The IC is ideal for use in the brightness
control (dimming) of lamps such as, in dashboard
applications. For a constant brightness the preselected
duty cycle can be reduced automatically as a function of
the supply voltage.
Features
D
Pulse width modulation up to 2 kHz clock frequency
D
Protection against short circuit, load-dump
overvoltage and reverse V
S
D
Interference and damage protection according to
VDE 0839 and ISO/TR 7637/1.
D
Duty cycle 0 to 100 % continuously
D
Output stage for power MOSFET
D
Charge pump noise suppressed
D
Ground wire breakage protection
Ordering Information
Extended Type Number
U6084B–FP
Package
SO16
Remarks
Block Diagram
C
5
V
S
16
9
Short circuit
latch monitoring
5
6
C
1
47 k
W
3
C
2
Control input
RC oscillator
PWM
Logic
Output
14
Charge
pump
13
C
3
47 nF
11
Current monitoring
+ short circuit detection
12
R
sh
V
Batt
Duty cycle
range
0–100%
Duty cycle
reduction
4
C
6
Voltage
monitoring
1
Enable/
disable
2
95 9751
150
W
R
3
Ground
Figure 1. Block diagram with external circuit
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
1 (8)
U6084B
Pin Description
GND
En / Dis
V
I
Reduct
1
2
3
4
16
15
14
13
12
11
10
9
95 9754
V
S
NC
Output
2 V
S
Sense
Delay
NC
Latch
Attenuation 5
Osc
NC
NC
6
7
8
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
GND
En / Dis
V
I
Reduct
NC
Osc
NC
NC
Latch
NC
Delay
Sense
2V
S
Output
NC
V
S
Function
IC ground
Enable/disable
Control input (duty cycle)
Duty cycle reduction
Attenuation
Oscillator
Not connected
Not connected
Status short circuit latch
Not connected
Short circuit protection delay
Current sensing
Voltage doubler
Output
Not connected
Supply voltage V
S
Functional Description
Pin1, GND
Ground-Wire Breakage
To protect the FET in the case of ground-wire breakage,
a 820 k
W
resistor between gate and source it is recom-
mended to provide proper switch-off conditions.
Pin 4, Duty Cycle Reduction
With Pin 4 connected according to figure 2, the set duty
12.5 V. This causes a
cycle is reduced as from V
Batt
power reduction in the FET and in the lamps. In addition,
the brightness of the lamps is largely independent of the
supply voltage range, V
Batt
= 12.5 to 16 V.
Output Slope Control
The rise and fall time (t
r
, t
f
) of the lamp voltage can be
limited to reduce radio interference. This is done with an
integrator which controls a power MOSFET as source fol-
lower. The slope time is controlled by an external
capacitor C4 and the oscillator current (see figure 2).
Calculation:
t
f
r
Pin 2, Enable/Disable
The dimmer can be switched on or off with pin 2 indepen-
dently of the set duty cycle.
V
2
Approx. >0.7 V or open
< 0.7 V or connected to Pin 1
Function
Disable
Enable
C
4
I
osc
With V
Batt
= 12 V, C
4
= 470 pF and I
osc
= 40
m
A,we thus
obtain a controlled slope of
Batt
+
t
+
V
r
Pin 3, Control Input
The pulse width is controlled by means of an external po-
tentiometer (47 k
W
). The characteristic (angle of
rotation/duty cycle) is linear. The duty cycle can be varied
from 0 to 100%. It is possible to further restrict the duty
cycle with the resistors R
1
and R
2
(see figure 2).
Pin 3 is protected against short-circuit to V
Batt
and ground
GND (V
Batt
16.5 V).
t
f
+
t
+
12 V
470 pF
40
m
A
+
141
m
s
Pin 5, Attenuation
Capacitor C
4
connected to Pin 5 damps oscillation
tendencies.
Pin 6, Oscillator
The oscillator determines the frequency of the output
voltage. This is defined by an external capacitor, C
2
. It is
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
x
2 (8)
U6084B
charged with a constant current, I, until the upper switch-
ing threshold is reached. A second current source is then
activated which taps a double current, 2 I, from the
charging current. The capacitor, C
2
, is thus discharged by
the current, I, until the lower switching threshold is
reached. The second source is then switched off again and
the procedure starts once more.
Example for Oscillator Frequency Calculation
V
T100
A selection of different values of C
2
and C
4
, provides a
range of oscillator frequency, f, from 10 to 2000 Hz.
Pins 7, 8, 10 and 15
Not connected.
+
V
V
¦
+
V
V
+
V
S
T 100
TL
S
S
+
(V
*
I
a
+
(V
*
I
a
+
(V
*
I
a
3
1
Batt
S
2
Batt
Batt
S
R
3
)
S
a
a
3
1
Pin 9, Status Short Circuit Latch
2
R
3
)
R
3
)
a
The status of the short-circuit latch can be monitored via
Pin 9 (open collector output).
Pin 9
L
H
Function
Short-circuit detected
No short-circuit detected
where
V
T100
+
High switching threshold (100% duty cycle)
V
T
t
100
V
TL
a
1
,
a
2
and
a
3
are fixed constant.
+
Low switching threshold
+
High switching threshold (
t
100% duty cycle)
Pins 11 and 12, Short-Circuit Protection
and Current Sensing
1. Short-Circuit Detection and Time Delay, t
d
The lamp current is monitored by means of an external
shunt resistor. If the lamp current exceeds the threshold
for the short-circuit detection circuit (V
T2
90 mV), the
duty cycle is switched over to 100% and the capacitor C
5
is charged by a current source of 20
m
A (I
ch
– I
dis
). The
external FET is switched off after the cut-off threshold
(V
T11
) is reached. Renewed switching on the FET is pos-
sible only after a power-on reset. The current source, I
dis,
ensures that the capacitor C
5
is not charged by parasitic
currents. The capacitor C
5
is discharged by I
dis
to typ.
0.7 V.
V
Batt
= 12 V, I
S
= 4 mA, R
3
= 150
W
,
a
1
= 0.7,
a
2
= 0.67 and
a
3
= 0.28.
V
T100
The above mentioned threshold voltages are calculated
for the following values given in the data sheet.
+
(12 V
*
4 mA 150
W
)
V
t
+
11.4 V 0.67
+
7.6 V
V
+
11.4 V 0.28
+
3.2 V
T 100
TL
0.7
[
8 V
For a duty cycle of 100%, an oscillator frequency, f, is
as follows:
f
+
2
+
2
+
2
I
osc
(V
T100
*
V
TL
)
C
2
, where C
2
22 nF
40
m
A
and I
osc
+
+
Therefore:
f
40
m
A
(8 V 3.2 V)
Time delay, t
d
, is as follows:
22 nF
*
+
189 Hz
t
d
+
C
@
(V
*
0.7 V) (I
*
I
5
T11
ch
dis
)
For a duty cycle of less than 100%, the oscillator fre-
quency, f, is as follows:
f
(V
T
t
100
*
I
osc
V
TL
) C
2
)
4
)
4
With C
5
= 330 nF and V
Batt
= 12 V, we have
V
Batt
C
4
t
d
12 V
470 pF
whereas
C
4
= 470 pF
7.6 V
+
2
+
185 Hz
*
3.2 V
40 A
22 nF
m
+
330 nF
@
(9.8 V
*
0.7 V) 20
m
A
+
150 ms.
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
3 (8)
U6084B
2. Current Limitation
The lamp current is limited by a control amplifier that
protects the external power transistor. The voltage drop
across an external shunt resistor acts as the measured vari-
able. Current limitation takes place for a voltage drop of
Owing
to
the
difference
V
T1
100 mV.
V
T1
–V
T2
10 mV, current limitation occurs only when
the short-circuit detection circuit has responded.
After a power-on reset, the output is inactive for half an
oscillator cycle. During this time , the supply voltage ca-
pacitor can be charged so that current limitation is
guaranteed in the event of a short circuit when the IC is
switched on for the first time.
Pin 16, Supply Voltage, V
s
or V
Batt
Undervoltage Detection:
In the event of voltages of approx. V
Batt
< 5.0 V, the ex-
ternal FET is switched off and the latch for short-circuit
detection is reset.
A hysteresis ensures that the FET is switched on again at
approximately V
Batt
5.4 V.
Overvoltage Detection
Stage 1
If overvoltages V
Batt
> 20 V (typ.) occur, the external
transistor is switched off and switched on again at
V
Batt
< 18.5 V (hysteresis).
Stage 2
If V
Batt
> 28.5 V (typ.), the voltage limitation of the IC
is reduced from 26 V to 20 V. The gate of the external
transistor remains at the potential of the IC ground, thus
producing voltage sharing between FET and lamps in the
event of overvoltage pulses occuring (e.g., load-dump).
The short-circuit protection is not in operation. At
V
Batt
< 23 V, the overvoltage detection stage 2 is
switched off.
Pins 13 and 14, Charge Pump and Output
Output, Pin 14, is suitable for controlling a power MOS-
FET. During the active integration phase, the supply
current of the operational amplifier is mainly supplied by
the capacitor C
3
(bootstrapping). Additionally, a trickle
charge is generated by an integrated oscillator
(f
13
400 kHz) and a voltage doubler circuit. This per-
mits a gate voltage supply at a duty cycle of 100%.
Absolute Maximum Ratings
Parameters
Junction temperature
Ambient temperature range
Storage temperature range
Symbol
T
j
T
amb
T
stg
Value
150
–40 to +110
–55 to +125
Unit
°C
°C
°C
Thermal Resistance
Parameters
Junction ambient
Symbol
R
thJA
Value
120
Unit
K/W
Electrical Characteristics
T
amb
= –40 to +110°C, V
Batt
= 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground,
unless otherwise specified (see figure 1). All other values refer to Pin GND (Pin 1).
Parameters
Current consumption
Supply voltage
Stabilized voltage
Battery undervoltage
detection
4 (8)
Test Conditions / Pins
Pin 16
Overvoltage detection,
stage 1
I
S
= 10 mA
Pin 16
– on
– off
Symbol
I
S
V
Batt
V
S
V
Batt
Min.
Typ.
Max.
6.8
25
27.0
5.6
6.0
Unit
mA
V
V
V
24.5
4.4
4.8
5.0
5.4
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
U6084B
Parameters
Test Conditions / Pins
Battery overvoltage detection
Pin 2
Stage 1:
– on
– off
Stage 2:
– on
– off
Stabilized voltage
I
S
= 30 mA
Pin 16
Short-circuit protection
Pin 12
Short-circuit current limita- V
T1
= V
S
– V
12
tion
Short-circuit detection
V
T2
= V
S
– V
12
Delay timer short circuit detection
Pin 11
Switched off threshold
V
T11
= V
S
– V
11
Charge current
Dicharge current
Capacitance current
I
5
= I
ch
– I
dis
Output short-circuit latch
Pin 9
Saturation voltage
I
9
= 100
m
A
Voltage doubler
Pin 13
Voltage
Duty cycle 100%
Oscillator frequency
Internal voltage limitation
I
13
= 5 mA
g
(whichever is lower)
Gate output
Pin 14
Voltage
g
Low level
V
Batt
= 16.5 V,
T
amb
= 110
°C,
R
3
= 150
W
High level,
duty cycle 100%
Current
V
14
= Low level
V
14
= High level, I
13
> | I
14
|
Symbol
V
Batt
V
Batt
V
Z
V
T1
V
T2
V
T1
– V
T2
Min.
18.3
16.7
25.5
19.5
18.5
85
75
3
9.5
Typ.
20.0
18.5
28.5
23.0
20.0
100
90
10
9.8
23
3
20
150
Max.
21.7
20.3
32.5
26.5
21.5
120
105
30
10.1
Unit
V
V
V
mV
mV
mV
V
m
A
m
A
mA
mV
V
T11
I
ch
I
dis
I
5
V
sat
V
13
f
13
V
13
V
13
V
14
13
27
350
2 V
S
280
26
(V
S+14
)
0.35
400
27.5
(V
S+15
)
0.70
520
30.0
(V
S+16
)
0.95
1.5 *)
kHz
V
V
V
14
I
14
1.0
–1.0
–20
6.9
10
0.68
0.65
0.26
26
6.0
V
13
mA
Enable/ Disable
Current
Duty cycle reduction
Z-voltage
Oscillator
Frequency
Threshold cycle
Upper
Pin 2
V
2
= 0 V
I
4
= 500
m
A
Pin 4
V
4
Pin6
V
T100
V
S
V
T
t
100
V
S
7.4
8.0
2000
0.72
0.69
0.3
54
13.5
I
2
–40
–60
m
A
V
Hz
V
14
V
14
Lower
Oscillator current
Frequency tolerance
*)
a
3
+
High,
a
+
+
Low,
a
+
+
V
V
1
2
TL
S
a
1
a
2
a
3
f
0.7
0.67
0.28
40
9.9
V
Batt
= 12 V
C
4
open, C
2
= 470 nF,
duty cycle = 50%
I
osc
f
m
A
Hz
Reference point is battery ground.
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
5 (8)
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