XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
DECEMBER 2009
REV. 1.0.0
GENERAL DESCRIPTION
The XR17V354
1
(V354) is a single chip 4-channel
PCI Express (PCIe) UART (Universal Asynchronous
Receiver and Transmitter), optimized for higher
performance and lower power. The V354 serves as a
single lane PCIe bridge to 4 indepedent enhanced
16550 compatible UARTs. The V354 is compliant to
PCIe 2.0 Gen 1 (2.5GT/s).
In addition to the UART channels, the V354 has 16
multi-purpose I/Os (MPIOs), a 16-bit general purpose
counter/timer and a global interrupt status register to
optimize interrupt servicing.
Each UART of the V354 has many enhanced
features such as the 256-bytes TX and RX FIFOs,
programmable Fractional Baud Rate Generator,
Automatic Hardware or Software Flow Control, Auto
RS-485 Half-Duplex Direction Control, programmable
TX and RX FIFO Trigger Levels, TX and RX FIFO
Level Counters, infrared mode, and data rates up to
25Mbps. The V354 is available in a 176-pin FPBGA
package (13 x 13 mm).
N
OTE
1:
Covered by U.S. Patents #5,649,122, #6,754,839,
#6,865,626 and #6,947,999
FEATURES
•
Single 3.3V power supply
•
Internal buck regulator for 1.2V core
•
PCIe 2.0 Gen 1 compliant
•
x1 Link, dual simplex, 2.5Gbps in each direction
•
Expansion bus interface
•
EEPROM interface for configuration
•
Data read/write burst operation
•
Global interrupt status register for all four UARTs
•
Up to 25 Mbps serial data rate
•
16 multi-purpose inputs/outputs (MPIOs)
•
16-bit general purpose timer/counter
•
Sleep mode with wake-up Indicator
•
Four independent UART channels controlled with
■
■
■
■
■
■
■
■
16550 compatible register Set
256-byte TX and RX FIFOs
Programmable TX and RX Trigger Levels
TX/RX FIFO Level Counters
Fractional baud rate generator
Automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis
Automatic Xon/Xoff software flow control
RS-485 half duplex direction control output
with programmable turn-around delay
Multi-drop with Auto Address Detection
Infrared (IrDA 1.1) data encoder/decoder
APPLICATIONS
•
Next generation Point-of-Sale Systems
•
Remote Access Servers
•
Storage Network Management
•
Factory Automation and Process Control
•
Multi-port RS-232/RS-422/RS-485 Cards
■
■
•
Software compatible to XR17C15x, XR17D15x,
XR17V25x PCI UARTs
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XR17V354
C o n f ig u r a t io n
S pace
R e g is t e r s
TX+
TX-
RX+
RX-
CLK+
CLK-
CLKREQ#
PERST#
EN485#
E N IR #
EECK
EEDI
EEDO
EECS
D [ 7 :0 ]
B u c k R e g u la to r
U AR T C hannel 0
2 5 6 - b y t e T X F IF O
64-
UART
R egs
TX & R X
TX & R X
T X [3 :0 ]
T X [7 :0 ]
R X [3 :0 ]
R X [ 7 :0 ]
R T S # [3 :0 ]
D T R # [ 3 :0 ]
IR
ENDEC
1 2 5 M H z C lo c k
BRG
2 5 6 - b y tte R X F IF O
6 4 - b y e R X F IF O
P C Ie
PC I Local
In t e r f a c e
Bus
In te r fa c e
G lo b a l
C o n fig u r a tio n
R e g is te r s
U AR T C hannel 1
U AR T C hannel 2
U AR T C hannel 3
2
C T S # [3 :0 ]
D S R # [3 :0 ]
D C D # [3 :0 ]
C o n f ig u r a t io n
Spa
O
E E P R
c e
M
R e g is t e r s
In te r fa c e
U AR T C hannel 3
U AR T C hannel 5
U AR T C hannel 6
M u lti- p u r p o s e
In A u tT /Oh a n u t s 7
U p R s C u tp n e l
R I# [ 3 : 0 ]
M P IO [ 1 5 : 0 ]
SEL
CLK
IN T
MODE
PRES
E x p a n s io n
In te r f a c e
1 6 - b it
T im e r /C o u n te r
- p u rp o s e
In p u ts /O u t p u t s
C r y s ta l O s c /B u ff e r
TM RCK
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
F
IGURE
2. 176-FPBGA P
INOUT
A1 Corner
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9 10 11 12 13 14 15
REV. 1.0.0
Transparent Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
MPIO0
MPIO2
MPIO5
GND
RX+
GND
TX+
GND
CLKREQ#
GND
MPIO9
MPIO10
NC
2
NC
NC
NC
MPIO1
MPIO4
TEST0
RX-
GND
TX-
VCC12
PERST#
MPIO8
MPIO12
MPIO13
RESET#
3
NC
NC
NC
NC
MPIO3
MPIO6
GND
REXT
GND
VCC33
MPIO7
MPIO11
MPIO15
TCK
TDI
4
GND
NC
NC
GND
VCC12
GND
CLK+
CLK-
GND
VCC12
GND
MPIO14
TRST
TDO
GND
5
NC
NC
NC
VCC33
6
NC
NC
NC
GND
7
DSR2#
CD2#
RI2#
VCC12
8
GND
DTR2#
CTS2#
GND
9
RTS2#
RX2
TX2
VCC33
10
TMRCK
ENIR#
EN485#
GND
11
TEST2
TEST1
FB
VCC12
12
GND
GND
GND
GND
VCC33
GND
VCC12
GND
VCC33
GND
VCC12
13
LX
VCC33
VCC33
PWRGD
D1
D5
SEL
RI1#
DTR1#
RTS1#
CD0#
RX0
TX0
EECK
NC
14
LX
VCC33
ENABLE
INT
D3
D6
CLK
PRES
DSR1#
RX1
RI0#
DSR0#
CTS0#
EEDI
EECS
15
NC
VCC33
D0
D2
D4
D7
MODE
GND
CD1#
CTS1#
TX1
GND
DTR0#
RTS0#
NC
TMS
TX3
RTS3#
RX3
GND
CTS3#
DTR3#
DSR3#
VCC33
CD3#
NC
NC
GND
RI3#
NC
GND
VCC12
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
EEDO
NC
NC
GND
ORDERING INFORMATION
P
ART
N
UMBER
XR17V354IB176-F
P
ACKAGE
176-FPBGA
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
D
EVICE
S
TATUS
In Development
2
XR17V354
REV. 1.0.0
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
PIN DESCRIPTIONS
N
AME
PCIe SIGNALS
CLK+
CLK-
TX+
TX-
RX+
RX-
CLKREQ#
PERST#
REXT
G4
H4
J1
J2
G1
G2
L1
L2
H3
I
I
O
O
I
I
O
I
PCIe reference clock input.
P
IN
#
T
YPE
D
ESCRIPTION
PCIe differential TX outputs
PCIe differential RX inputs
PCIe edge connector clock request
PCIe edge connector reset
Connect a 191 ohm 1% resistor to GND. This is used for PCIe PHY calibra-
tion.
MODEM OR SERIAL I/O INTERFACE
TX0
RX0
N13
M13
O
I
UART channel 0 Transmit Data or infrared transmit data.
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted internally prior to
decoding by setting FCTR bit [4].
UART channel 0 Request to Send or general purpose output (active LOW).
UART channel 0 Clear to Send or general purpose input (active LOW).
UART channel 0 Data Terminal Ready or general purpose output (active
LOW).
UART channel 0 Data Set Ready or general purpose input (active LOW).
UART channel 0 Carrier Detect or general purpose input (active LOW).
UART channel 0 Ring Indicator or general purpose input (active LOW).
UART channel 1 Transmit Data or infrared transmit data.
UART channel 1 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
UART channel 1 Request to Send or general purpose output (active LOW).
UART channel 1 Clear to Send or general purpose input (active LOW).
UART channel 1 Data Terminal Ready or general purpose output (active
LOW).
UART channel 1 Data Set Ready or general purpose input (active LOW).
UART channel 1 Carrier Detect or general purpose input (active LOW).
UART channel 1 Ring Indicator or general purpose input (active LOW).
UART channel 2 Transmit Data or infrared transmit data.
RTS0#
CTS0#
DTR0#
DSR0#
CD0#
RI0#
TX1
RX1
P15
N14
N15
M14
L13
L14
L15
K14
O
I
O
I
I
I
O
I
RTS1#
CTS1#
DTR1#
DSR1#
CD1#
RI1#
TX2
K13
K15
J13
J14
J15
H13
C9
O
I
O
I
I
I
O
3
XR17V354
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.0
PIN DESCRIPTIONS
N
AME
RX2
P
IN
#
B9
T
YPE
I
D
ESCRIPTION
UART channel 2 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
UART channel 2 Request to Send or general purpose output (active LOW).
UART channel 2 Clear to Send or general purpose input (active LOW).
UART channel 2 Data Terminal Ready or general purpose output (active
LOW).
UART channel 2 Data Set Ready or general purpose input (active LOW).
UART channel 2 Carrier Detect or general purpose input (active LOW).
UART channel 2 Ring Indicator or general purpose input (active LOW).
UART channel 3 Transmit Data or infrared transmit data.
UART channel 3 Receive Data or infrared receive data. Normal RXD input
idles at HIGH condition. The infrared pulses can be inverted prior to decoding
by setting FCTR bit [4].
UART channel 3 Request to Send or general purpose output (active LOW).
UART channel 3 Clear to Send or general purpose input (active LOW).
UART channel 3 Data Terminal Ready or general purpose output (active
LOW).
UART channel 3 Data Set Ready or general purpose input (active LOW).
UART channel 3 Carrier Detect or general purpose input (active LOW).
UART channel 3 Ring Indicator or general purpose input (active LOW).
RTS2#
CTS2#
DTR2#
DSR2#
CD2#
RI2#
TX3
RX3
A9
C8
B8
A7
B7
C7
N5
R5
O
I
O
I
I
I
O
I
RTS3#
CTS3#
DTR3#
DSR3#
CD3#
RI3#
P5
N6
P6
R6
N7
N8
O
I
O
I
I
I
EXPANSION INTERFACE
MODE
G15
I
Expansion Interface Mode Select. Connect this pin to VCC to enable master
mode or when there is no slave device. Connect this pin to GND when the
device is in slave mode.
Expansion Interface Clock. In master mode, this pin is the clock output to the
slave device. In slave mode, this pin is the clock input from the master
device. The expansion interface clock is 62.5MHz. The UARTs on the slave
device will need to use different baud rate generator divisors than the master
device. The trace capacitance between the master and slave device must be
less than 25pF.
Expansion Interface Data 7 (MSB). The trace capacitance between the mas-
ter and slave device must be less than 25pF.
Expansion Interface Data 6. The trace capacitance between the master and
slave device must be less than 25pF.
Expansion Interface Data 5. The trace capacitance between the master and
slave device must be less than 25pF.
Expansion Interface Data 4. The trace capacitance between the master and
slave device must be less than 25pF.
CLK
G14
I/O
D7
D6
D5
D4
F15
F14
F13
E15
I/O
I/O
I/O
I/O
4
XR17V354
REV. 1.0.0
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
PIN DESCRIPTIONS
N
AME
D3
D2
D1
D0
SEL
P
IN
#
E14
D15
E13
C15
G13
T
YPE
I/O
I/O
I/O
I/O
I/O
D
ESCRIPTION
Expansion Interface Data 3. The trace capacitance between the master and
slave device must be less than 25pF.
Expansion Interface Data 2. The trace capacitance between the master and
slave device must be less than 25pF.
Expansion Interface Data 1. The trace capacitance between the master and
slave device must be less than 25pF.
Expansion Interface Data 0 (LSB). The trace capacitance between the master
and slave device must be less than 25pF.
Expansion Interface Read/Write Select. This is the the read/write select input
in the slave mode. This is the read/write select output in the master mode.
This pin must be left unconnected if there is no slave device. The trace
capacitance between the master and slave device must be less than 25pF.
Expansion Interface Interrupt. This is the expansion interface interrupt output
in the slave mode. This is the expansion interface interrupt input in the mas-
ter mode. This pin must be left unconnected if there is no slave device. The
trace capacitance between the master and slave device must be less than
25pF.
Slave Present. In master mode, connect this pin to VCC if there is a slave
device present. Connect this pin to GND to disable access to the slave
device (slave device may or may not be present). In slave mode, this pin
should be connected to GND.
INT
D14
I/O
PRES
H14
I
MPIO SIGNALS
MPIO0
MPIO1
MPIO2
MPIO3
MPIO4
MPIO5
MPIO6
MPIO7
MPIO8
MPIO9
C1
D2
D1
E3
E2
E1
F3
L3
M2
N1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Multi-purpose input/output 0. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT
Multi-purpose input/output 1. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 2. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 3. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 4. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 5. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 6. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 7. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 8. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT
Multi-purpose input/output 9. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
5
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