SI5023-EVB datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Development board/suite/development tools> SI5023-EVB

SI5023-EVB: Descriptionclock & timer development tools snt/sdh gbe 2.7gbps oc48/12/3 stm16/4/1; CategoryDevelopment board/suite/development tools; File Size2MB，28 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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SI5023-EVB Overview

clock & timer development tools snt/sdh gbe 2.7gbps oc48/12/3 stm16/4/1

SI5023-EVB Parametric

Parameter Name	Attribute value
Manufacture	Silicon Laboratories
Product Category	Clock & Timer Development Tools
RoHS	Yes

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Si5023

ULTI

-R

ATE

SONET/SDH CDR IC

WITH

IMITING

MPLIFIER

Features

igh-speed clock and data recovery device with integrated limiting amp:



Supports OC-48/12/3, STM-16/4/



Bit error rate alarm

1, Gigabit Ethernet, and 2.7 Gbps



Reference and referenceless

FEC

operation supported



Loss-of-signal level alarm



DSPLL technology



Data slicing level control



Jitter generation 3.0 mUI

rms



10 mV

differential sensitivity

(TYP)



Small footprint: 5 x 5 mm



3.3 V supply

Ordering Information:

See page 25.

Applications



BER_ALM

CLKOUT+

Description

RATESEL0

CLKOUT–

CLKDSBL

BERMON

BER_LVL

SONET/SDH/ATM routers



Add/drop multiplexers



Digital cross connects



Gigabit Ethernet interfaces



SONET/SDH test equipment



Optical transceiver modules



SONET/SDH regenerators



Board level serial links

Pin Assignments

Si5023

VDD

REXT

RESET/CAL

VDD

DOUT+

DOUT–

GND

The Si5023 is a fully-integrated, high-performance limiting amp and clock

and data recovery (CDR) IC for high-speed serial communication systems.

It derives timing information and data from a serial input at OC-48/12/3,

STM-16/4/1, or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data

streams is also provided for OC-48/STM-16 applications that employ

forward error correction (FEC). Use of an external reference clock is

optional. Silicon Laboratories DSPLL

technology eliminates sensitive

noise entry points, thus making the PLL less susceptible to board-level

interaction and helping to ensure optimal jitter performance.

The Si5023 represents a new standard in low jitter, low power, small size,

and integration for high-speed LA/CDRs. It operates from a 3.3 V supply

over the industrial temperature range (–40 to 85 °C).

RATESEL1

LOS_LVL

SLICE_LVL

REFCLK+

REFCLK–

LOL

GND

Pad

LOS

DIN+

DIN–

LTR

VDD

Top View

Functional Block Diagram

LOS_LVL

LOS

Signal

Detect

Retimer

DSQLCH

BUF

DOUT+

DOUT–

DIN+

DIN–

Limiting

Amp

DSPLL

BER

Monitor

BUF

CLKOUT+

CLKOUT–

CLK_DSBL

REFCLK+

REFCLK–

(Optional)

Lock

Detection

Bias Gen.

Reset/

Calibration

BER_ALM

REXT

BERMON

SLICE_LVL

LTR

BER_LVL

LOL

RATESEL

RESET/CAL

Rev. 1.3 6/08

DSQLCH

VDD

Si5023

Si5023

ABLE

Section

ONTENTS

Page

1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.2. DSPLL

® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.3. Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

4.4. Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.5. Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.6. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.7. Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.8. Loss-of-Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.9. Bit Error Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.10. Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.11. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.12. RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.13. Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.14. Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.15. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.16. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.17. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.18. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.19. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5. Pin Descriptions: Si5023 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Rev. 1.3

SI5023-EVB Related Products

	SI5023-EVB	Si5023-D-GM	SI5023-D-GMR
Description	clock & timer development tools snt/sdh gbe 2.7gbps oc48/12/3 stm16/4/1	clock synthesizer / jitter cleaner snt/sdh gbe 2.7gbps oc48/12/3 stm16/4/1	clock synthesizer / jitter cleaner limiting amp 3.3 V
Is it Rohs certified?	-	conform to	conform to
Maker	-	Silicon Laboratories Inc	Silicon Laboratories Inc
Parts packaging code	-	QFN	QFN
package instruction	-	HVQCCN,	HVQCCN,
Contacts	-	28	28
Reach Compliance Code	-	unknow	unknow
JESD-30 code	-	S-XQCC-N28	S-XQCC-N28
length	-	5 mm	5 mm
Number of functions	-	1	1
Number of terminals	-	28	28
Maximum operating temperature	-	85 °C	85 °C
Minimum operating temperature	-	-40 °C	-40 °C
Package body material	-	UNSPECIFIED	UNSPECIFIED
encapsulated code	-	HVQCCN	HVQCCN
Package shape	-	SQUARE	SQUARE
Package form	-	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Certification status	-	Not Qualified	Not Qualified
Maximum seat height	-	0.9 mm	0.9 mm
Nominal supply voltage	-	3.3 V	3.3 V
surface mount	-	YES	YES
Telecom integrated circuit types	-	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT	ATM/SONET/SDH CLOCK RECOVERY CIRCUIT
Temperature level	-	INDUSTRIAL	INDUSTRIAL
Terminal form	-	NO LEAD	NO LEAD
Terminal pitch	-	0.5 mm	0.5 mm
Terminal location	-	QUAD	QUAD
width	-	5 mm	5 mm

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