Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 5
Release Information ..................................................................................................................................... 5
Device Support............................................................................................................................................. 5
Chapter 2. Functional Description ........................................................................................................ 6
Key Concepts........................................................................................................................................................ 6
Block Diagram....................................................................................................................................................... 6
Deinterlacing Algorithms ....................................................................................................................................... 7
Weave .......................................................................................................................................................... 7
Bob............................................................................................................................................................... 7
Intra Motion Adaptive Deinterlacing ............................................................................................................. 7
Inter Motion Adaptive Deinterlacing ............................................................................................................. 7
Frame Rate Conversion ........................................................................................................................................ 8
Dynamic Parameters Updating ............................................................................................................................. 8
Memory Bandwidth and Size ................................................................................................................................ 9
Primary I/O .......................................................................................................................................................... 10
Interface Descriptions ......................................................................................................................................... 11
Video Input/Output ..................................................................................................................................... 11
Memory Interface ....................................................................................................................................... 11
Parameter Register Read/Write Interface .................................................................................................. 12
Timing Specifications .......................................................................................................................................... 13
Video Input/Output Timing ......................................................................................................................... 13
Video Frame Timing................................................................................................................................... 15
Memory Interface Timing ........................................................................................................................... 16
Dynamic Parameters Updating .................................................................................................................. 17
Chapter 3. Parameter Settings ............................................................................................................ 18
Architecture ......................................................................................................................................................... 19
Frame Dimensions ..................................................................................................................................... 19
Filter Physical Characteristics .................................................................................................................... 20
I/O Specification .................................................................................................................................................. 20
Implementation.................................................................................................................................................... 21
Chapter 4. IP Core Generation and Evaluation .................................................................................. 22
Licensing the IP Core.......................................................................................................................................... 22
Getting Started .................................................................................................................................................... 22
Configuring the Deinterlacer IP Core in IPexpress ............................................................................................. 22
IPexpress-Created Files and Top-Level Directory Structure...................................................................... 24
Instantiating the Core ................................................................................................................................. 25
Running Functional Simulation .................................................................................................................. 25
Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 26
Hardware Evaluation........................................................................................................................................... 27
Enabling Hardware Evaluation in Diamond................................................................................................ 27
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 27
Updating/Regenerating the IP Core .................................................................................................................... 27
Regenerating an IP Core in Diamond ........................................................................................................ 27
Regenerating an IP Core in ispLEVER ...................................................................................................... 28
Chapter 5. Support Resources ............................................................................................................ 29
Lattice Technical Support.................................................................................................................................... 29
E-mail Support ........................................................................................................................................... 29
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Deinterlacer IP Core User’s Guide
Table of Contents
Local Support ............................................................................................................................................. 29
Internet ....................................................................................................................................................... 29
References.......................................................................................................................................................... 29
Revision History .................................................................................................................................................. 29
Appendix A. Resource Utilization ....................................................................................................... 30
LatticeECP2 and LatticeECP2S Devices ............................................................................................................ 30
Ordering Part Number................................................................................................................................ 30
LatticeECP2M and LatticeECP2MS Devices ...................................................................................................... 30
Ordering Part Number................................................................................................................................ 30
LatticeECP3 Devices .......................................................................................................................................... 31
Ordering Part Number................................................................................................................................ 31
LatticeXP2 Devices ............................................................................................................................................. 31
Ordering Part Number................................................................................................................................ 31
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Deinterlacer IP Core User’s Guide
Chapter 1:
Introduction
The Lattice Deinterlacer IP core converts interlaced video into progressive video format using bob, intra or inter
motion adaptive deinterlacing algorithms to reduce interline flickers and jagged edges. The Deinterlacer IP core
supports image sizes up to 4kx4k with YCbCr 4:2:2, 4:4:4 and RGB video formats. The Deinterlacer IP core sup-
ports dynamic parameter updating via a parameter bus which can be configured to operate on a different clock
from the core. Simple frame rate conversion is employed to support different input and output frame rates.
Quick Facts
Table 1-1
gives quick facts about the Deinterlacer IP core.
Table 1-1. Deinterlacer IP Core Quick Facts
Deinterlacer IP Core Configuration
PAL720x576 YCbCr4:2:2
Core
Requirements
FPGA Families Supported
Minimum Device Required
Targeted Device
Algorithms
Resource
Utilization
Registers
LUTs
EBRs
Core
Requirements
FPGA Families Supported
Minimum Device Required
Targeted Device
Algorithms
Resource
Utilization
Registers
LUTs
EBRs
Core
Requirements
FPGA Families Supported
Minimum Device Required
Targeted Device
Algorithms
Resource
Utilization
Registers
LUTs
EBRs
Lattice Implementation
Design Tool
Support
Synthesis
Simulation
Intra
2612
3144
4
Inter
3825
4702
7
Intra
2609
3127
4
Inter
3833
4690
7
LatticeXP2™
LFXP2-8E
LFXP2-40E-7F484C
Intra
2657
3223
6
Inter
3916
4774
11
Intra
2612
3144
4
Inter
3825
4702
7
LFE3-17EA
LFE3-70EA-8FN1156C
Intra
2656
3167
6
Inter
3916
4734
11
1080 60I to 1080 60P YCbCR4:2:2
LatticeECP2™
LFE2-12E
LFE2-50E-7F484C
Intra
2657
3223
6
LatticeECP3™
Inter
3916
4774
11
Lattice Diamond
®
1.3 or ispLEVER
®
8.1 SP1
Synopsys
®
Synplify™ Pro for Lattice E-2011.03L
Aldec
®
Active-HDL™ 8.2 SP1 Lattice Edition
Mentor Graphics
®
ModelSim™ SE 6.3F
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Deinterlacer IP Core User’s Guide
Introduction
Features
The Deinterlacer IP core supports the following features:
• Single-color, YCbCr 4:2:2, YcbCr 4:4:4 and RGB video formats
• Serial and parallel deinterlacing
• Weave, bob, intra and inter motion adaptive deinterlacing algorithms
• Frame rate conversion
• Configurable initial field
• Configurable thresholds for inter motion adaptive deinterlacing algorithm
• Dynamic parameter update of frame size, initial field and bypass mode
• Configurable parameter bus width
• Configurable parameters bus clock
• Configurable memory bus width and base address
• Configurable memory burst length and burst count
• Configurable internal FIFO type and depth
• 8, 10 or 12-bit color depth per plane
• Configurable line buffer type
Release Information
• Deinterlacer IP core version 1.0
• Last updated August 17, 2011
Device Support
• LatticeECP2™, LatticeECP2M, LatticeECP2MS, LatticeECP2S, LatticeECP3, LatticeXP2
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Deinterlacer IP Core User’s Guide
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