CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4.
θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For
θ
JC
, the “case temp” location is taken at the package top center.
6.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
7. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
8. Device temperature is closely tied to data-rates, driver loads and overall pin activity. Review “Power Dissipation Considerations” on page 6 for
more information.
Recommended Operating Conditions
PARAMETER
Device Power
Comparator Output High Rail
Comparator Output Low Rail
Common Mode Input Voltage Range
Ambient Temperature
Junction Temperature
SYMBOL
V
CC
-V
EE
V
OH
V
OL
V
CM
T
A
T
J
MIN
10
V
EE
+1
V
EE
+0.5
V
EE
-40
27
TYP
15
MAX
18
V
CC
-0.5
V
EE
+6
V
CC
-5
+85
+125
UNITS
V
V
V
V
°C
°C
Electrical Specifications
Test Conditions: V
CC
= 12V, V
EE
= -3V, V
OH
= 5V, V
OL
= 0V, PD = V
EE
, C
LOAD
= 15pF
,
T
A
= 25°C, unless
otherwise specified.
SYMBOL
TEST CONDITIONS
MIN
(Note 13)
TYP
MAX
(Note 13)
UNITS
PARAMETER
DC CHARACTERISTICS
Input Offset Voltage
Input Bias Current
Power-down Current
Power-down Time (Note 11)
Power-up Time (Note 11)
TIMING CHARACTERISTICS
Propagation Delay
Rise Time (Note 11)
Fall Time (Note 11)
Propagation Delay Mismatch
Maximum Operating Frequency
Min Pulse Width
COMPARATOR INPUT
Input Current
V
OS
I
BIAS
I
PD
t
PD
t
PU
CV
AX
= CV
BX
= 1.5V
V
INPX
- CV
(A/B)X
= ±5V
PD = V
CC
-50
10
8
10
15
50
25
25
mV
nA
µA
µs
µs
t
pd
t
r
t
f
Δt
pd
F
MAXR
t
WIDR
Symmetry 50%
4.0
9.5
1.4
1.5
0.5
65
7.7
15
ns
ns
ns
2
ns
MHz
ns
I
IN
V
INPX
= V
CC
or V
EE
-100
0
100
nA
4
FN6230.3
April 4, 2013
ISL55141, ISL55142, ISL55143
Electrical Specifications
Test Conditions: V
CC
= 12V, V
EE
= -3V, V
OH
= 5V, V
OL
= 0V, PD = V
EE
, C
LOAD
= 15pF
,
T
A
= 25°C, unless
otherwise specified.
(Continued)
SYMBOL
C
IN
TEST CONDITIONS
MIN
(Note 13)
TYP
2.5
MAX
(Note 13)
UNITS
pF
PARAMETER
Input Capacitance (Note 11)
DIGITAL OUTPUTS Q
AX
, Q
BX
Output Resistance
Output Logic High Voltage
Output Logic Low Voltage
RoutR
V
OH
V
OL
V
OH
= 5V, I
SOURCE
= 1mA
V
OL
= 0V, I
SINK
= 1mA
18
4.9
0.00
27
4.95
0.05
37
5.0
0.1
Ω
V
V
POWER SUPPLIES, STATIC CONDITIONS
Positive Supply DC Current/Comparator
Negative Supply Current/Comparator
Total Power Dissipation/Comparator
NOTES:
9. Lab characterization, room temperature, timing parameters matched stimulus/loads, channel-to-channel skew < 500ps, 1ns maximum by design
10. Note about I
CC
measurement input can approach 140mA (single comparator) at maximum pattern rates
11. Limits should be considered typical and are not production tested.
12. Total Power dissipation per comparator can be approximately calculated from the following:
P = (V
CC
-V
EE
)*8.25mW + 90pF*(V
CC
-V
EE
)^2*f + C
L
*(V
CC
-V
EE
)^2*f, where f is the operating frequency and C
L
is the load capacitance.
Because the ISL55142 has two comparators, the power dissipation would be twice of P calculated from this equation. The ISL55143 would be
four times P.
13. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
I
CC
I
EE
No input data
No input data
-12.5
+8.25
-8.25
670
12.5
mA
mA
mW
P (Note 12) Input data at 40MHz
Test Circuits and Waveforms
DATA = 1
DATA = 0
400mV
0V
t
PDLH
t
PDHL
V
OH
(≈V
H
)
Q
AX
, Q
BX
t
R
50%
50%
V
OL
(≈V
L
)
t
F
V
INPX
FIGURE 1. COMPARATOR PROPAGATION DELAY AND TRANSITION TIME MEASUREMENT POINTS
CV
A
2.4V
V
INP
+
-
V
CC
Q
A
Although there is no electrical difference between the CV
A
and CV
B
Inputs, if one defines CV
A
as being the high
threshold and CV
B
being the low threshold, it becomes
easier to understand the utilization of a dual threshold
comparator. Essentially this enables the qualification of an
incoming signal into three states. In Figure 2, the three
states are Valid Low <0.4V, No-man’s-land (between 0.4
and 2.4V), Valid High >2.4V. Table 2 shows how the Q
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