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UA R T U S I I D E S I G N S O F T WA R E
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Fastest Path to Your Design
Quartus® II software is number one in performance and productivity for CPLD,
FPGA, and SoC designs, providing the fastest path to convert your concept into
reality. Quartus II software can easily adapt to your specific needs in all phases of
FPGA and CPLD design in different platforms.
Quartus II software provides everything you need to design with Altera devices:
• Qsys system integration tool
• TimeQuest timing analyzer
• Transceiver Toolkit
• External Memory Interface Toolkit
• PowerPlay power analysis tools
• DSP Builder Advanced Blockset
• Altera SDK for OpenCL
TM
• ModelSim®-Altera Edition simulation software
Quartus II Software Key Features
Faster
Compile Time
PowerPlay
Power Analyzer
TimeQuest
Timing Analyzer
Qsys
System-Level
Integration Tool
Industry-Leading Compile Time
Quartus II software delivers superior synthesis and placement and routing, resulting
in compilation time advantages for both Web Edition and Subscription Edition software.
Additional compilation time reduction features include the following:
– Multiprocessor support
– Incremental compile
– Advanced place-and-route algorithms
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Compile Time Comparison
Quartus II Software Relative Compilation Time
(Relative time based on fixed designs and fixed CPU)
100%
Relative Compile Time (Log Scale)
50%
25%
13%
6%
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
Year
Compare Full and Incremental Compile
Full Compilation
Incremental Compilation
Top-Down Approach
Create Design Partitions (A, B, C)
Step 1
Quartus II Project
(No Partitions)
Quartus II Project
Step 1
A
A
B
B
C
C
Modify Design
(in Red)
Re-compile Whole Project
Step 2
Quartus II Project
(No Partitions)
Step 2
Modify Design in Partition A
Re-compile Only Partition A
Quartus II Project
A
A
B
B
C
C
Incremental Compile
• Compiles only the changes in a partition to reduce compile time by up to 70 percent
• Preserves timing in unchanged partitions for performance preservation
• Enables team-based designs
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TimeQuest Timing Analyzer
TimeQuest Timing Analyzer GUI
• Comprehensive Synopsys® Design
Constraints (SDC) support
• Second-generation, easy-to-use timing
analyzer
• Complete GUI environment and scripting
support to create timing constraints and
reports
• Easy-to-use wizard to create SDC
constraints
PowerPlay Power Analyzer Flow
Design
Entry
Constraints
Speed
Area
Power
PowerPlay Power Analyzer
• Push-button power optimization technology
• Automated power optimization for an average
10 percent reduction in power consumption
Synthesis
Placement and
Routing
Optimize Power
PowerPlay
Power Analyzer
Power-Optimized Design
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Qsys System Integration Tool
The Qsys system integration tool saves significant time and effort in the FPGA design process by
automatically generating interconnect logic to connect intellectual property (IP) functions and
subsystems. Qsys is powered by a new FPGA-optimized network-on-a-chip (NoC) technology,
delivering higher performance, improved design reuse, and faster verification.
• High-performance Qsys interconnect based on the NoC architecture and automatic pipelining
delivers up to 2X higher performance
• Hierarchical design flow enables scalable designs, supports team-based design, and maximizes
design reuse
• Higher flexibility with support for mixing different industry-standard interfaces, such as the AMBA®
AXI™, AMBA APB
TM
, AMBA AHB
TM
, and Avalon® interfaces
• IP management capabilities enable designs and systems to appear as an IP for easier reuse
• Faster board bring-up with a system-level debug approach using address-based transactions and
System Console
Qsys – Altera’s System Integration Tool
High-
Performance
Interconnect
Hierarchy
IP Management
Industry-Standard
Interface
Real-Time
System Debug
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