Table of Contents
Chapter 1. Introduction .......................................................................................................................... 3
Quick Facts ........................................................................................................................................................... 3
Features ................................................................................................................................................................ 3
Release Information .............................................................................................................................................. 3
Device Support...................................................................................................................................................... 3
Chapter 2. Functional Description ........................................................................................................ 4
Key Concepts........................................................................................................................................................ 4
Block Diagram....................................................................................................................................................... 4
Primary I/O ............................................................................................................................................................ 4
Timing Specifications ............................................................................................................................................ 5
Chapter 3. Parameter Settings .............................................................................................................. 7
Implementation...................................................................................................................................................... 8
Chapter 4. IP Core Generation............................................................................................................... 9
Licensing the IP Core............................................................................................................................................ 9
Getting Started ...................................................................................................................................................... 9
Configuring the Divider IP Core in IPexpress........................................................................................................ 9
IPexpress-Created Files and Top Level Directory Structure...................................................................... 12
Instantiating the Core ................................................................................................................................. 13
Running Functional Simulation .................................................................................................................. 13
Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 13
Hardware Evaluation........................................................................................................................................... 14
Updating/Regenerating the IP Core .................................................................................................................... 14
Regenerating an IP Core in Diamond ........................................................................................................ 14
Chapter 5. Support Resources ............................................................................................................ 16
Lattice Technical Support.................................................................................................................................... 16
Online Forums............................................................................................................................................ 16
Telephone Support Hotline ........................................................................................................................ 16
E-mail Support ........................................................................................................................................... 16
Local Support ............................................................................................................................................. 16
Internet ....................................................................................................................................................... 16
References.......................................................................................................................................................... 16
.Revision History ................................................................................................................................................. 16
Appendix A. Resource Utilization ....................................................................................................... 17
LatticeECP3 Devices .......................................................................................................................................... 17
Ordering Part Number................................................................................................................................ 17
LatticeECP2M Devices ....................................................................................................................................... 17
Ordering Part Number................................................................................................................................ 17
LatticeECP2 Devices .......................................................................................................................................... 17
Ordering Part Number................................................................................................................................ 18
LatticeXP2 Devices ............................................................................................................................................. 18
Ordering Part Number................................................................................................................................ 18
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG108_01.0, June 2012
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Divider IP Core User’s Guide
Chapter 1:
Introduction
The Divider IP core is a one-clock divider which completes one integer division every clock. It supports signed or
unsigned inputs and provides configurable output latency.
Quick Facts
Table 1-1. Divider IP Core Quick Facts
Divider IP Core Configuration
FPGA Families Supported
Core Requirements
Minimum Device Required
Targeted Device
Configuration
Resource Utilization
Registers
LUTs
Slices
Configuration
Resource Utilization
Registers
LUTs
Slices
Configuration
Resource Utilization
Registers
LUTs
Slices
Lattice Implementation
Design Tool Support
Synthesis
Simulation
LatticeECP3™
LFE3-17EA
LFE3-35EA-8FN672C
828
311
446
586
409
409
3127
1459
1791
LatticeECP2/M
LFE2-6E
LFE2-35E-7F672C
828
311
446
586
409
409
3123
1459
1788
Lattice Diamond
®
2.0
Synopsys
®
Synplify™ Pro for Lattice F-2012.03L
Aldec
®
Active-HDL™ 9.1 Lattice Edition
Mentor Graphics
®
ModelSim™ SE 6.3F
LatticeXP2™
LFXP2-5E
LFXP2-30E-7F672C
886
368
484
619
442
431
3137
1458
1791
20-bit numerator, 10-bit denominator, 20 output latency
24-bit numerator, 12-bit denominator, 12 output latency
32-bit numerator, 32-bit denominator, 32 output latency
Features
• Supports signed or unsigned numerator and denominator
• Supports numerator and denominator data width 4-64
• Supports forced positive remainder
• Supports configurable output latency
• Optional clock enable and data valid ports
Release Information
• Divider IP Core version 1.0
– Last updated May, 2012
Device Support
• , LatticeECP3, LatticeECP2M™, LatticeECP2™ and LatticeXP2 FPGA Families
IPUG108_01.0, June 2012
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Divider IP Core User’s Guide
Chapter 2:
Functional Description
Key Concepts
The Divider IP core implements integer division with the formula:
Numerator = Denominator * Quotient + Remainder
Numerator and Denominator can be signed or unsigned integers. When either the Numerator or Denominator is a
signed integer, Quotient and Remainder will also be in signed integer format. When the Remainder is configured to
be “Always Positive Remainder”, the Remainder will be a positive signed integer value.
Block Diagram
Figure 2-1. Divider IP Core Block Diagram
0
1-bit Division
1
1-bit Division
2
1-bit Division
N-3
1-bit Division
N-2
1-bit Division
N-1
1-bit Division
N stages
The Divider IP core uses a non-restoring division algorithm to implement the integer division operation.
There are N stages of 1-bit division in an integer division operation, where N is the width of the quotient.
Each stage generates a 1-bit quotient and partial-remainder. In the last stage, the final quotient and remainder are
generated. 1-bit division uses an adder-subtracter to compare the partial remainder and denominator to get a new
partial remainder. Quotient-digit selection is based on the sign of the partial remainder. In the last stage, the partial
remainder is corrected to get the final remainder.
The Divider IP core supports configurable output latency. The latency can be any number of clock cycles from 1 to
N. When latency is set to the value M, M stages of output registers are uniformly distributed into the N stages of 1-
bit division operation. The final division stage always has output registers.
Primary I/O
Figure 2-2. Divider IP Core I/O Diagram
rstn
clk
ce
dvalid_in
numerator
denominator
Divider
IP Core
dvalid_out
quotient
remainder
IPUG108_01.0, June 2012
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Divider IP Core User’s Guide
Functional Description
Table 2-1. Primary I/O Descriptions
Port
General I/Os
rstn
clk
ce
dvalid_in
numerator
denominator
dvalid_out
quotient
remainder
1
1
1
1
4-64
4-64
1
4-64
4-64
I
I
I
I
I
I
O
O
O
Asynchronous active-low reset signal
Input clock
Clock enable, active high
Optional input data valid signal, active-high
Input numerator value
Input denominator value
Optional output data valid signal, active high
Output quotient
Output remainder
Size
I/O
Description
Timing Specifications
The Divider IP core is a one-clock divider. It can accept a numerator and denominator every clock cycle and gener-
ate a quotient and remainder every clock cycle.
When the input numerator and denominator are in an unsigned format, the output quotient and remainder are in an
unsigned format. When either the numerator or denominator is in a signed format, the output quotient and remain-
der are always in a signed format.
Figure 2-3. Unsigned Integer Division with a Latency of 8
clk
dvalid_in
numerator
denominator
64
1
63
2
62
3
61
4
60
5
59
6
58
7
57
8
56
9
55
10
54
11
53
12
52
13
51
14
50
15
49
16
Latency = 8
dvalid_out
quotient
remainder
64
0
31
1
20
2
15
1
12
0
9
5
8
2
7
1
Figure 2-4. Signed Integer Division with a Latency of 8
clk
dvalid_in
numerator
denominator
64
-1
-63
2
62
3
-61
-4
-60
-5
59
-6
-58
7
57
-8
56
-9
-55
10
54
-11
-53
12
52
-13
-51
14
50
15
49
16
Latency = 8
dvalid_out
quotient
remainder
-64
0
-31
-1
20
2
15
-1
12
0
-9
5
-8
-2
-7
1
IPUG108_01.0, June 2012
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Divider IP Core User’s Guide
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