SW-QUARTUS-SE-FIX datasheet, PDF

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SW-QUARTUS-SE-FIX: Descriptiondevelopment software fixed license for quartus II; CategoryDevelopment board/suite/development tools; File Size2MB，136 Pages; ManufacturerAltera (Intel); Environmental Compliance

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development software fixed license for quartus II

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Parameter Name	Attribute value
Manufacture	Alte
Product Category	Development Software
RoHS	Not Applicable
Produc	Subscriptions
For Use With	CPLDs, FPGAs, HardCopy ASICs
Description/Functi	Fixed license for Windows

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Introduction to the

Quartus

II Software

Version

10.0

Introduction to the Quartus II Software

Altera, the Altera logo, HardCopy, MAX, MAX+PLUS, MAX+PLUS II, MegaCore, MegaWizard, Nios, OpenCore,

Quartus, Quartus II, the Quartus II logo, and SignalTap are registered trademarks of Altera Corporation in the

United States and other countries. Avalon, ByteBlaster, ByteBlasterMV, Cyclone, Excalibur, IP MegaStore, Jam,

LogicLock, MasterBlaster, SignalProbe, Stratix, and USB-Blaster are trademarks and/or service marks of Altera

Corporation in the United States and other countries. Product design elements and mnemonics used by Altera

Corporation are protected by copyright and/or trademark laws.

Altera Corporation acknowledges the trademarks and/or service marks of other organizations for their

respective products or services mentioned in this document, specifically: ARM is a registered trademark and

AMBA is a trademark of ARM, Limited. Mentor Graphics and ModelSim are registered trademarks of Mentor

Graphics Corporation.

Altera reserves the right to make changes, without notice, in the devices or the device specifications identified in

this document. Altera advises its customers to obtain the latest version of device specifications to verify, before

placing orders, that the information being relied upon by the customer is current. Altera warrants performance

of its semiconductor products to current specifications in accordance with Altera’s standard warranty. Testing

and other quality control techniques are used to the extent Altera deems such testing necessary to support this

warranty. Unless mandated by government requirements, specific testing of all parameters of each device is not

necessarily performed. In the absence of written agreement to the contrary, Altera assumes no liability for Altera

applications assistance, customer’s product design, or infringement of patents or copyrights of third parties by or

arising from use of semiconductor devices described herein. Nor does Altera warrant or represent any patent

right, copyright, or other intellectual property right of Altera covering or relating to any combination, machine,

or process in which such semiconductor devices might be or are used.

Altera products are not authorized for use as critical components in life support devices or systems without the

express written approval of the president of Altera Corporation. As used herein:

1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body

or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions

for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to

perform can be reasonably expected to cause the failure of the life support device or system, or

to affect its safety or effectiveness.

Altera products are protected under numerous U.S. and foreign patents and pending

applications, maskwork rights, and copyrights.

Contents

Preface ............................................................................................................................................vii

Chapter 1: Design Flow.................................................................................................................. 1

Introduction....................................................................................................................... 2

Graphical User Interface Design Flow .......................................................................... 3

Command-Line Executables ........................................................................................... 7

Using Standard Command-Line Commands & Scripts ............................. 10

Using Tcl Commands ...................................................................................... 12

Design Methodologies and Planning .......................................................................... 14

Incremental Design Flows .............................................................................. 14

Using LogicLock Regions ............................................................................... 15

Using LogicLock Regions in Incremental Compilation Flows.................. 16

Chapter 2: Design Entry............................................................................................................... 19

Introduction..................................................................................................................... 20

Creating a Project............................................................................................................ 21

Creating a Design ........................................................................................................... 22

Using the Quartus II Block Editor ................................................................. 22

Using the Quartus II Symbol Editor.............................................................. 22

Using the Quartus II Text Editor.................................................................... 23

Using Verilog HDL, VHDL, & AHDL........................................................... 23

Using the State Machine Editor ..................................................................... 24

Using Altera Megafunctions......................................................................................... 24

Using Intellectual Property (IP) Megafunctions.......................................... 25

Using the MegaWizard Plug-In Manager..................................................... 27

Instantiating Megafunctions in the Quartus II Software............................ 27

Instantiation in Verilog HDL & VHDL........................................... 28

Using the Port & Parameter Definition .......................................... 28

Inferring Megafunctions................................................................... 28

Instantiating Megafunctions in EDA Tools .................................................. 28

Using the Black Box Methodology.................................................. 29

Instantiation by Inference................................................................. 29

Using the Clear Box Methodology.................................................. 29

Constraint Entry ............................................................................................................. 31

Using the Assignment Editor ......................................................................... 32

Using the Pin Planner...................................................................................... 33

The Settings Dialog Box .................................................................................. 35

Making Timing Constraints............................................................................ 36

Creating Design Partitions.............................................................................. 36

Creating Design Partitions with the Design Partitions Planner................ 37

Chapter 3: Synthesis ..................................................................................................................... 39

Introduction..................................................................................................................... 40

Using Quartus II Verilog HDL & VHDL Integrated Synthesis................................ 41

Using Quartus II Synthesis Netlist Optimization Options ........................ 43

Using the Design Assistant to Check Design Reliability .......................................... 44

Analyzing Synthesis Results With the Netlist Viewers ............................................ 45

LTERA

ORPORATION

NTRODUCTION

TO THE

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II S

OFTWARE

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III

ABLE

ONTENTS

The RTL Viewer ................................................................................................ 45

The State Machine Viewer .............................................................................. 47

The Technology Map Viewer.......................................................................... 48

Chapter 4: Place and Route.......................................................................................................... 51

Introduction..................................................................................................................... 52

Using Incremental Compilation ................................................................................... 53

Analyzing Fitting Results .............................................................................................. 54

Using the Messages Window to View Fitting Results ................................ 55

Using the Report Window or Report File to View Fitting Results............ 56

Using the Chip Planner to Analyze Results ................................................. 56

Using the Design Assistant to Check Design Reliability............................ 58

Optimizing the Fit .......................................................................................................... 58

Using Location Assignments.......................................................................... 58

Setting Options that Control Place & Route................................................. 59

Setting Fitter Options ........................................................................ 59

Setting Physical Synthesis Optimization Options ........................ 59

Setting Individual Logic Options that Affect Fitting.................... 60

Using the Resource Optimization Advisor .................................................. 60

Using the Design Space Explorer................................................................... 63

Chapter 5: Timing Analysis and Design Optimization ........................................................... 65

Introduction..................................................................................................................... 66

Running the TimeQuest Timing Analyzer.................................................................. 66

Specifying Timing Constraints......................................................... 68

Viewing Timing Information for a Path........................................................ 70

Viewing Timing Delays with the Technology Map Viewer ....................... 72

Timing Closure................................................................................................................ 73

Using the Chip Planner ................................................................................... 74

Chip Planner Tasks And Layers ...................................................... 74

Making Assignments......................................................................... 74

Using the Timing Optimization Advisor...................................................... 75

Using Netlist Optimizations to Achieve Timing Closure........................... 75

Using LogicLock Regions to Preserve Timing ............................................. 77

Using the Design Space Explorer to Achieve Timing Closure .................. 78

Power Analysis with the PowerPlay Power Analyzer ............................... 78

PowerPlay Early Power Estimator Spreadsheets ........................................ 80

Chapter 6: Programming & Configuration ............................................................................... 83

Introduction..................................................................................................................... 84

Creating and Using Programming Files...................................................................... 85

Chapter 7: Debugging and Engineering Change Managment ............................................... 89

Introduction..................................................................................................................... 90

Using the SignalTap II Logic Analyzer........................................................................ 91

Analyzing SignalTap II Data........................................................................... 92

Using an External Logic Analyzer ............................................................................... 93

■

NTRODUCTION

TO THE

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II S

OFTWARE

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ORPORATION

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