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X9252TV24I-2.7

Description
Quad Digitally-Controlled (XDCP) potentiometer
Categoryaccessories   
File Size128KB,21 Pages
ManufacturerXicon Passive Components
Websitehttp://www.xicor.com
Download Datasheet Compare View All

X9252TV24I-2.7 Overview

Quad Digitally-Controlled (XDCP) potentiometer

New Feature
Dual Interface
Low Power + Quad 256-tap +
2-Wire bus + Up/Down interface
Quad Digitally-Controlled (XDCP
TM
) Potentiometer
FEATURES
• Quad solid state potentiometer
• 256 wiper tap points–0.4% resolution
• 2-wire serial interface for Write, Read, and
transfer operations of the potentiometer
• Up/down interface for individual potentiometers
• Wiper resistance: 40
typical
• Non-volatile storage of wiper positions
• Power On Recall. Loads saved wiper position on
Power-Up.
• Standby current < 20µA Max
• Maximum wiper current: 3mA
• V
CC
: 2.7V to 5.5V operation
• 2.8k
,
10k
, 50k
,
100k
version of total pot
resistance
• Endurance: 100, 000 data changes per bit per
register
• 100 yr. data retention
• 24-Lead TSSOP
DESCRIPTION
X9252
The X9252 integrates 4 digitally controlled potentio-
meters (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are imple-
mented using 255 resistive elements in a series array.
Between each pair of elements are tap points con-
nected to wiper terminals through switches. The posi-
tion of each wiper on the array is controlled by the user
through the Up/Down (U/D) or 2-wire bus interface.
The wiper of each potentiometer has an associated
volatile Wiper Counter Register (WCR) and four non-
volatile Data Registers (DRs) that can be directly writ-
ten to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. At power-up, the device recalls
the contents of the default data registers DR00, DR10,
DR20, DR30, to the corresponding WCR.
Each DCP can be used as a three-terminal potentio-
meter or as a two terminal variable resistor in a wide
variety of applications including the programming of
bias voltages, the implementation of ladder networks,
and three resistor programmable networks.
FUNCTIONAL DIAGRAM
V
CC
A2
A1
A0
SDA
SCL
Up-Down
Interface
POWER UP,
INTERFACE
CONTROL
AND
STATUS
2-Wire
Interface
WCR0
DR00
DR01
DR02
DR03
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
R
H0
R
H1
R
H2
R
H3
DS0
DS1
CS
U/D
V
SS
WP
R
W0
R
L0
R
W1
R
L1
R
W2
R
L2
R
W3
R
L3
REV 1.4.1 7/29/03
www.xicor.com
1 of 21

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