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CAT24AC128GWI-1.8TE13

Description
128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins
Categorystorage    storage   
File Size473KB,11 Pages
ManufacturerCatalyst
Websitehttp://www.catalyst-semiconductor.com/
Environmental Compliance
Download Datasheet Parametric View All

CAT24AC128GWI-1.8TE13 Overview

128kbit I2C Serial CMOS EEPROM With Three Chip Address Input Pins

CAT24AC128GWI-1.8TE13 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerCatalyst
package instructionSOP, SOP8,.25
Reach Compliance Codeunknow
Data retention time - minimum100
Durability1000000 Write/Erase Cycles
I2C control byte1010DDDR
JESD-30 codeR-PDSO-G8
memory density131072 bi
Memory IC TypeEEPROM
memory width8
Number of terminals8
word count16384 words
character code16000
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize16KX8
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialSERIAL
power supply2/5 V
Certification statusNot Qualified
Serial bus typeI2C
Maximum standby current0.000001 A
Maximum slew rate0.003 mA
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
write protectHARDWARE
CAT24AC128
128kbit I
2
C Serial CMOS EEPROM With Three Chip Address Input Pins
FEATURES
I
400kHz (2.5V) and 100kHz (1.8V) I
2
C bus
I
Commercial, industrial and extended
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
compatibility
I
1.8 to 5.5 volt operation
I
Low power CMOS technology
I
Schmitt trigger filtered inputs for noise
automotive temperature ranges
I
Write protect feature
– Entire array protected when WP at V
IH
I
1,000,000 program/erase cycles
I
100 year data retention
I
8-Pin DIP, 8-Pin SOIC (JEDEC/EIAJ) or
suppression
I
64-Byte page write buffer
I
Self-timed write cycle with auto-clear
14-pin TSSOP
DESCRIPTION
The CAT24AC128 is a 128kbit Serial CMOS EEPROM
internally organized as 16,384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24AC128
features a 64-byte page write buffer. The device operates
via the I
2
C bus serial interface and is available in 8-pin
DIP, 8-pin SOIC or 14-pin TSSOP packages. Three
device address inputs allows up to 8 devices to share a
common 2-wire I
2
C bus.
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
BLOCK DIAGRAM
EXTERNAL LOAD
SOIC Package (J, K, W, X)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
512
SDA
START/STOP
LOGIC
DOUT
ACK
SENSE AMPS
SHIFT REGISTERS
TSSOP Package (U14, Y14)
A0
A1
NC
NC
NC
A2
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V CC
WP
NC
NC
NC
SCL
SDA
XDEC
WP
CONTROL
LOGIC
256
E
2
PROM
256X512
PIN FUNCTIONS
Pin Name
SDA
SCL
WP
V
CC
V
SS
A0 - A2
Function
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +5.5V Power Supply
Ground
Device Address Inputs
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
HIGH VOLTAGE/
TIMING CONTROL
DATA IN STORAGE
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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