DISCRETE SEMICONDUCTORS
DATA SHEET
PSMN070-200B; PSMN070-200P
N-channel TrenchMOS
(TM)
transistor
Product specification
August 1999
Philips Semiconductors
Product specification
N-channel TrenchMOS
(TM)
transistor
FEATURES
•
’Trench’
technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
g
PSMN070-200B; PSMN070-200P
QUICK REFERENCE DATA
SYMBOL
d
V
DSS
= 200 V
I
D
= 35 A
R
DS(ON)
≤
70 mΩ
s
GENERAL DESCRIPTION
SiliconMAX
products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in
each package at each voltage rating.
Applications:-
• d.c. to d.c. converters
• switched mode power supplies
The PSMN070-200P is supplied in the SOT78 (TO220AB) conventional leaded package.
The PSMN070-200B is supplied in the SOT404 surface mounting package.
PINNING
PIN
1
2
3
tab
gate
drain
1
source
drain
DESCRIPTION
SOT78 (TO220AB)
tab
SOT404 (D
2
PAK)
tab
2
1 23
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
I
D
I
DM
P
D
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
- 55
MAX.
200
200
±
20
35
25
140
250
175
UNIT
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin:2 of the SOT404 package
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
(TM)
transistor
AVALANCHE ENERGY LIMITING VALUES
PSMN070-200B; PSMN070-200P
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
Non-repetitive avalanche
energy
Non-repetitive avalanche
current
CONDITIONS
Unclamped inductive load, I
AS
= 35 A;
t
p
= 100
µs;
T
j
prior to avalanche = 25˚C;
V
DD
≤
50 V; R
GS
= 50
Ω;
V
GS
= 10 V; refer
to fig:15
MIN.
-
MAX.
462
UNIT
mJ
I
AS
-
35
A
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
TYP.
-
SOT78 package, in free air
SOT404 package, pcb mounted, minimum
footprint
60
50
MAX.
0.6
-
-
UNIT
K/W
K/W
K/W
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
GS(TO)
R
DS(ON)
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate threshold voltage
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
Drain-source on-state
V
GS
= 10 V; I
D
= 17 A
resistance
Gate source leakage current V
GS
=
±10
V; V
DS
= 0 V
Zero gate voltage drain
V
DS
= 200 V; V
GS
= 0 V;
current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
T
j
= 175˚C
T
j
= 175˚C
MIN.
200
178
2.0
1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
3.0
-
-
60
-
2
0.05
-
77
16
28
22
100
80
90
3.5
4.5
7.5
4570
370
160
-
-
4.0
-
6
70
203
100
10
500
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
mΩ
mΩ
nA
µA
µA
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
pF
pF
pF
I
D
= 35 A; V
DD
= 160 V; V
GS
= 10 V
V
DD
= 100 V; R
D
= 2.7
Ω;
V
GS
= 10 V; R
G
= 5.6
Ω
Resistive load
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
(TM)
transistor
PSMN070-200B; PSMN070-200P
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
CONDITIONS
MIN.
-
-
-
-
-
TYP. MAX. UNIT
-
-
0.85
160
1.0
35
140
1.2
-
-
A
A
V
ns
µC
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
I
F
= 25 A; V
GS
= 0 V
Reverse recovery time
Reverse recovery charge
I
F
= 20 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= 30 V
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS
(TM)
transistor
PSMN070-200B; PSMN070-200P
Normalised Power Derating, PD (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
150
Mounting Base temperature, Tmb (C)
175
1
Transient thermal impedance, Zth j-mb (K/W)
D = 0.5
0.2
0.1
0.1
0.05
0.02
P
D
single pulse
T
0.01
tp
D = tp/T
0.001
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Drain Current, ID (A)
Tj = 25 C
35
30
25
5V
20
15
10
5
4.2 V
4.8 V
4.6 V
4.4 V
8V
VGS = 10V
6V
5.2 V
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
40
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VDS (V)
1.6
1.8
2
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); V
GS
≥
10 V
Peak Pulsed Drain Current, I
DM
(A)
1000
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
)
0.2
0.18
RDS(on) = VDS/ ID
100
tp = 10 us
Drain-Source On Resistance, RDS(on) (Ohms)
4.4 V
4.2 V
4.6 V
Tj = 25 C
0.16
0.14
0.12
100 us
0.1
0.08
5V
5.2 V
6V
VGS = 10V
4.8 V
10
D.C.
1 ms
10 ms
100 ms
1
1
10
100
Drain-Source Voltage, VDS (V)
1000
0.06
0.04
0.02
0
0
5
10
15
20
25
Drain Current, ID (A)
30
35
8V
40
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
)
August 1999
5
Rev 1.000
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