Data Sheet No. PD94701
IRU3138
SYNCHRONOUS PWM CONTROLLER
FOR TERMINATION POWER SUPPLY APPLICATIONS
FEATURES
1A Peak Output Drive Capability
0.8V Precision Reference Voltage Available
Shuts off both drivers at shorted output
and shutdown
200KHz to 400KHz operation set by an external
resistor
Soft-Start Function
Uncommitted Error Amplifier available for DDR
voltage tracking application
Protects the output when control FET is shorted
Synchronous Controller in 14-Pin Package
DESCRIPTION
The IRU3138 controller IC is designed to provide a low
cost synchronous Buck regulator for voltage tracking
applications such DDR memory and general purpose
on-board DC to DC converter. Modern micro processors
combined with DDR memory, need high-speed bandwidth
data bus which requires a particular bus termination volt-
age. This voltage will be tightly regulated to track the
half of chipset voltage for best performance. The IRU3138
together with two N-channel MOSFETs, provide a low
cost solution for such applications. This device features
a programmable frequency set from 200KHz to 400KHz,
under-voltage lockout for both Vcc and Vc supplies, an
external programmable soft-start function as well as
output under-voltage detection that latches off the de-
vice when an output short is detected.
APPLICATIONS
DDR memory source sink Vtt application
Graphic Card
Low cost on-board DC to DC such as
5V to 3.3V, 2.5V or 1.8V
TYPICAL APPLICATION
5V
V
DDQ
(2.5V)
C1
0.1uF
12V
C2
1uF
C3
2x 47uF
L1
1uH
C4
47uF
DDR
Memory
R1
1K
Vcc
V
REF
V
P
Vc
HDrv
Q1
IRF7460
D1
BAT54
L2
3.3uH
R2
1K
SS/SD
C5
0.1uF
U1
IRU3138
LDrv
PGnd
Fb
Vtt
1.25V @ 10A
C6
2x 150uF
40m
V
Q2
IRF7456
Rt
Comp
C7
3300pF
R3
13K
Gnd
Figure 1 - Typical application of IRU3138 when V
TT
tracks the V
DDQ
.
PACKAGE ORDER INFORMATION
T
A
(°C)
0 To 70
DEVICE
IRU3138CS
PACKAGE
14-Pin Plastic SOIC NB (S)
Rev. 1.0
01/29/04
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1
IRU3138
ABSOLUTE MAXIMUM RATINGS
V
CC
Supply Voltage .................................................. -0.5V - 25V
V
C
Supply Voltage .................................................... -0.5V - 25V
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 125°C
CAUTION:
Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device.
PACKAGE INFORMATION
14-PIN PLASTIC SOIC NB (S)
Fb 1
V
P
2
V
REF
3
Vcc 4
NC 5
LDrv 6
Gnd 7
14 NC
13 SS/SD
12 Comp
11 Rt
10 Vc
9 HDrv
8 PGnd
u
JA
=888C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V
CC
=5V, V
C
=12V and T
A
=0 to 70°C. Typical values refer
to T
A
=25°C. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient
temperature.
PARAMETER
Reference Voltage
V
REF
Voltage
Fb Voltage Line Regulation
UVLO
UVLO Threshold - V
CC
UVLO Hysteresis - V
CC
UVLO Threshold - V
C
UVLO Hysteresis - V
C
UVLO Threshold - Fb
UVLO Hysteresis - Fb
Supply Current
V
CC
Dynamic Supply Current
V
C
Dynamic Supply Current
V
CC
Static Supply Current
V
C
Static Supply Current
Soft-Start Section
Charge Current
Oscillator
Frequency
Ramp Amplitude
SYM
V
FB
L
REG
TEST CONDITION
MIN
0.784
TYP
0.8
MAX
0.816
1.6
4.5
3.65
0.5
UNITS
V
mV
V
V
V
V
V
V
mA
mA
mA
mA
mA
KHz
V
Rev. 1.0
01/29/04
5<V
CC
<12
4.0
3.0
0.3
4.25
0.25
3.5
0.25
0.4
0.02
6.5
11
4
2.5
15
180
360
20
200
400
1.25
UVLO Vcc
Supply Ramping Up
UVLO Vc
UVLO Fb
Supply Ramping Up
Fb Ramping Down
Note 1
Freq=200KHz, C
L
=3000pF
Freq=200KHz, C
L
=3000pF
SS=0V
SS=0V
SS=0V
Rt=Open
Rt=Gnd
Note 1
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Dyn Icc
Dyn Ic
I
CCQ
I
CQ
SS
IB
Freq
V
RAMP
8
14
6
4
26
220
440
2
IRU3138
PARAMETER
Error Amp
Fb Voltage Input Bias Current
Fb Voltage Input Bias Current
V
P
Voltage Range
Transconductance
Output Drivers
Rise Time
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
SYM
I
FB1
I
FB2
GM
Tr
T
f
T
DB
Ton
Toff
TEST CONDITION
SS=3V, Fb=1V
SS=0V, Fb=1V
MIN
TYP
0.1
50
MAX
UNITS
mA
mA
V
mmho
ns
ns
ns
%
%
0.7
500
C
LOAD
=3000pF
C
LOAD
=3000pF
Fb=0.7V, Freq=200KHz
Fb=1.5V
85
800
35
35
100
90
1.5
1000
70
70
0
Note 1:
Guaranteed by design, but not tested in production.
PIN DESCRIPTIONS
PIN#
1
2
3
4
PIN SYMBOL
PIN DESCRIPTION
Fb
This pin is connected directly to the output of the switching regulator via resistor divider to
provide feedback to the Error amplifier.
V
P
Non-inverting input of error amplifier.
V
REF
Reference Voltage.
V
CC
This pin provides biasing for the internal blocks of the IC as well as power for the low side
driver. A minimum of 1mF, high frequency capacitor must be connected from this pin to
ground to provide peak drive current capability.
NC
No Connection.
LDrv
Gnd
PGnd
Output driver for the synchronous power MOSFET.
Analog ground for internal reference and control circuitry. Connect to PGnd with a short
trace.
This pin serves as the separate ground for MOSFET's drivers and should be connected to
system's ground plane. A high frequency capacitor (0.1mF to 1mF) must be connected
from V
CC
and V
C
pins to this pin for noise free operation.
Output driver for the high side power MOSFET. This pin should not go negative (below
ground), this may cause problem for the gate drive circuit. It can happen when the inductor
current goes negative (Source/Sink), soft-start at no load and for the fast load transient
from full load to no load. To prevent negative voltage at gate drive, a low forward voltage
drop diode might be connected between this pin and ground.
This pin is connected to a voltage that must be at least 4V higher than the bus voltage of
the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A
minimum of 1mF, high frequency capacitor must be connected from this pin to ground to
provide peak drive current capability.
The switching frequency can be Programmed between 200KHz and 400KHz by connect-
ing a resistor between Rt and Gnd. Floating the pin set the switching frequency to 200KHz
and grounding the pin set the switching frequency to 400KHz.
Compensation pin of the error amplifier. An external resistor and capacitor network is
typically connected from this pin to ground to provide loop compensation.
This pin provides soft-start for the switching regulator. An internal current source charges
an external capacitor that is connected from this pin to ground which ramps up the output
of the switching regulator, preventing it from overshooting as well as limiting the input
current. The converter can be shutdown by pulling this pin below 2.8V.
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5
14
6
7
8
9
HDrv
10
V
C
11
Rt
12
Comp
13
SS / SD
Rev. 1.0
01/29/04
3
IRU3138
BLOCK DIAGRAM
Vcc 4
0.8V
1.25V
POR
4.25V
11 Rt
10 Vc
Rt
20uA
Oscillator
3.5V
64uA Max
Error Comp
POR
R
Reset Dom
25K
V
P
2
25K
Fb 1
0.4V
FbLo Comp
2.8V
8 PGnd
7 Gnd
Comp 12
POR
SS
Error Amp
6 LDrv
Q
Vcc
Ct
S
SS/SD 13
9 HDrv
0.25V
Bias
Generator
3V
1.25V
V
REF
3
3V
Vc
0.2V
Figure 2 - Simplified block diagram of the IRU3138.
4
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Rev. 1.0
01/29/04
IRU3138
THEORY OF OPERATION
Introduction
The IRU3138 is a fixed frequency, voltage mode syn-
chronous controller and consists of a precision refer-
ence voltage, an error amplifier, an internal oscillator, a
PWM comparator, 1A peak gate driver, soft-start and
shutdown circuits (see Block Diagram). The output volt-
age of the synchronous converter is set and controlled
by the output of the error amplifier; this is the amplified
error signal from the sensed output voltage and the refer-
ence voltage. This voltage is compared to a fixed fre-
quency linear sawtooth ramp and generates fixed fre-
quency pulses of variable duty-cycle, which drives the
two N-channel external MOSFETs.The timing of the IC
is provided through an internal oscillator circuit which
uses on-chip capacitor. The oscillation frequency is pro-
grammable between 200KHz to 400KHz by using an
external resistor. Figure 4A shows switching frequency
vs. external resistor.
Soft-Start
The IRU3138 has a programmable soft-start to control
the output voltage rise and limit the current surge at the
start-up. To ensure correct start-up, the soft-start se-
quence initiates when the Vc and Vcc rise above their
threshold (3.5V and 4.25V respectively) and generates
the Power On Reset (POR) signal. Soft-start function
operates by sourcing an internal current to charge an
external capacitor to about 3V. Initially, the soft-start func-
tion clamps the E/A’s output of the PWM converter and
disables the short circuit protection. During the power
up, the output starts at zero and voltage at Fb is below
0.4V. The feedback UVLO is disabled during this time
by injecting a current (64mA) into the Fb. This generates
a voltage about 1.6V (64mA325K) across the negative
input of E/A and positive input of the feedback UVLO
comparator (see Fig3).
20uA
SS/SD
3V
The magnitude of this current is inversely proportional to
the voltage at soft-start pin.
The 20mA current source starts to charge up the exter-
nal capacitor. In the mean time, the soft-start voltage
ramps up, the current flowing into Fb pin starts to de-
crease linearly and so does the voltage at the positive
pin of feedback UVLO comparator and the voltage nega-
tive input of E/A.
When the soft-start capacitor is around 1V, the current
flowing into the Fb pin is approximately 32mA. The volt-
age at the positive input of the E/A is approximately:
32mA325K = 0.8V
The E/A will start to operate and the output voltage starts
to increase. As the soft-start capacitor voltage contin-
ues to go up, the current flowing into the Fb pin will keep
decreasing. Because the voltage at pin of E/A is regu-
lated to reference voltage 0.8V, the voltage at the Fb is:
V
FB
= 0.8-25K3(Injected Current)
The feedback voltage increases linearly as the injecting
current goes down. The injecting current drops to zero
when soft-start voltage is around 2V and the output volt-
age goes into steady state.
As shown in Figure 4, the positive pin of feedback UVLO
comparator is always higher than 0.4V, therefore, feed-
back UVLO is not functional during soft-start.
Output of UVLO
POR
3V
≅
2V
≅
1V
Soft-Start
Voltage
Current flowing
into Fb pin
0V
64uA
0uA
64uA
Max
HDrv
POR
Comp
25K
0.8V
25K
Fb
Error Amp
LDrv
Voltage at negative input
of Error Amp and Feedback
UVLO comparator
≅
1.6V
0.8V
0.8V
0V
Voltage at Fb pin
0.4V
64uA
3
25K=1.6V
When SS=0
POR
Feeback
UVLO Comp
Figure 4 - Theoretical operational waveforms
during soft-start.
Figure 3 - Soft-start circuit for IRU3138.
Rev. 1.0
01/29/04
www.irf.com
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