NXP Semiconductors
Technical Data
Document Number: MC33912
Rev. 10.0, 8/2016
LIN system basis chip with dc motor
pre-driver and current sense
The 33912G5/BAC is a Serial Peripheral Interface (SPI) controlled System Basis
Chip (SBC), combining many frequently used functions in an MCU based
system, plus a Local Interconnect Network (LIN) transceiver. The 33912 has a
5.0 V, 50 mA/60 mA low dropout regulator with full protection and reporting
features. The device provides full SPI readable diagnostics and a selectable
timing watchdog for detecting errant operation. The LIN Protocol Specification
2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry which can be
disabled for higher data rates.
Two 50 mA/60 mA high-side switches and two 150 mA/160 mA low-side
switches with output protection are available. All outputs can be pulse-width
modulated (PWM). Four high voltage inputs are available for use in contact
monitoring, or as external wake-up inputs. These inputs can be used as high
voltage Analog Inputs. The voltage on these pins is divided by a selectable ratio
and available via an analog multiplexer.
The 33912 has three main operating modes: Normal (all functions available),
Sleep (V
DD
off, wake-up via LIN, wake-up inputs (L1-L4), cyclic sense and forced
wake-up), and Stop (V
DD
on with limited current capability, wake-up via CS, LIN
bus, wake-up inputs, cyclic sense, forced wake-up and external reset).
The 33912 is compatible with LIN Protocol Specification 2.0, 2.1, and SAEJ2602-
2. This device is powered using SMARTMOS technology.
Features
• Full-duplex SPI interface at frequencies up to 4.0 MHz
• LIN transceiver capable of up to 100 kbps with wave shaping
• Current sense module
• Four high voltage analog/logic Inputs
• Configurable window watchdog
• Switched/protected 5.0 V output (used for Hall sensors)
• Two 50 mA high-side and two 150 mA/160 mA low-side protected switches
• 5.0 V low drop regulator with fault detection and low voltage reset (LVR)
circuitry
V
BAT
33912
SYSTEM BASIS CHIP WITH LIN
2
ND
GENERATION
AC SUFFIX (Pb-FREE)
98ASH70029A
32-PIN LQFP
Applications
• Door module: window
• Lift, mirror, door lock, seat control switch
• Seat position motors, occupancy sensor
• Rain and light sensor, light control, sun roof
• Wiper, turning light, cruise control
• Climate: small motors, control panel
• Engine control: sensors, small motors
33912
VS1
VS2
VSENSE
HS1
L1
L2
L3
L4
LIN INTERFACE
LIN
VDD
PWMIN
ADOUT0
ADOUT1
MOSI
MISO
SCLK
CS
RXD
TXD
IRQ
RST
LS1
M
MCU
LS2
ISENSEH
ISENSEL
HVDD
HS2
WDCONF
Figure 1. 33912 simplified application diagram
© 2016 NXP B.V.
LGND
PGND
AGND
MC33912G5AC / MC34912G5AC
1
Orderable parts
The 33912G5 data sheet is within
MC33912G5 product specifications, Pages 3 to 52
The 33912BAC data sheet is within
MC33912BAC product specifications, Pages 53 to 103
Table 1. Orderable part variations
Part number
(1)
MC33912G5AC
Temperature (T
A
)
-40 to 125 °C
Package
Generation
Changes
1. Increase ESD Gun IEC61000-4-2 (gun test contact with 150 pF,
330 ohm test conditions) performance to achieve
±6.0
kV min on the
LIN pin.
2.5
32-LQFP
2. Immunity against ISO7637 pulse 3b
3. Reduce EMC emission level on LIN
4. Improve EMC immunity against RF - target new specification including
3x68pF
5. Comply with J2602 conformance test
MC33912BAC
MC34912BAC
-40 to 125 °C
-40 to 85 °C
2.0
Initial release
MC34912G5AC
-40 to 85 °C
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
33912
2
NXP Semiconductors
MC33912G5AC / MC34912G5AC
4
4.1
Pin connections
Pinout diagram
VSENSE
AGND
HVDD
VDD
29
NC
27
26
32
RXD
TXD
MISO
MOSI
SCLK
CS
ADOUT0
PWMIN
1
2
3
4
5
6
7
8
25
31
30
28
HS1
VS1
VS2
24
23
22
21
20
19
18
17
HS2
L1
L2
L3
L4
LS1
PGND
LS2
10
IRQ
11
12
13
14
15
16
ISENSEL
ADOUT1
RST
WDCONF
Figure 3. 33912 pin connections
A functional description of each pin can be found in the
Functional pin description
section beginning on
page 23.
Table 2. 33912 pin definitions
Pin
1
2
3
4
5
6
7
8
9
Pin name
RXD
TXD
MISO
MOSI
SCLK
CS
ADOUT0
PWMIN
RST
Formal name
Receiver Output
Transmitter Input
SPI Output
SPI Input
SPI Clock
SPI Chip Select
Analog Output Pin 0
PWM Input
Internal Reset I/O
Definition
This pin is the receiver output of the LIN interface which reports the state of the bus
voltage to the MCU interface.
This pin is the transmitter input of the LIN interface which controls the state of the bus
output.
SPI (Serial Peripheral Interface) data output. When CS is high, pin is in the high-
impedance state.
SPI (Serial Peripheral Interface) data input.
SPI (Serial Peripheral Interface) clock Input.
SPI (Serial Peripheral Interface) chip select input pin. CS is active low.
Analog Multiplexer Output.
High-side and Low-side Pulse Width Modulation Input.
Bidirectional Reset I/O pin - driven low when any internal reset source is asserted. RST
is active low.
ISENSEH
LIN
LGND
9
33912
NXP Semiconductors
5
FPGA/CPLD
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