- Guaranteed output tri-state while one power supply is "off"
and the other is "on"
- 1MΩ minimum input impedance power-off
• 0.6μm
CRH CMOS Technology
•
Operational Environment:
- Total dose: 100 krads(Si)
- Single Event Latchup immune
•
High speed, low power consumption
•
Schmitt trigger inputs to filter noisy signals
•
Available QML Q or V processes
•
Standard Microcircuit Drawing 5962-98580
- Device Types 06 and 07
•
Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640), wgt 1.4 grams
DESCRIPTION
The 16-bit wide UT54ACS164245SEI MultiPurpose transceiv-
er is built using Aeroflex’s CRH technology. This high speed,
low power UT54ACS164245SEI transceiver is designed to per-
form multiple functions including: asynchronous two-way
communication, schmitt input buffering, voltage translation,
cold and warm sparing. With either or both V
DD1
and V
DD2
are
equal to zero volts, the UT54ACS164245SEI outputs and inputs
present a minimum impedance of 1MΩ making it ideal for "cold
spare" applications. Balanced outputs and low "on" output im-
pedance make the UT54ACS164245SEI well suited for driving
high capacitance loads and low impedance backplanes. The
UT54ACS164245SEI enables system designers to interface 3.3
volt CMOS compatible components with 5 volt CMOS compo-
nents. For voltage translation, the A port interfaces with the 3.3
volt bus; the B port interfaces with the 5 volt bus. The direction
control (DIRx) controls the direction of data flow. The output
enable (OEx) overrides the direction control and disables both
ports. These signals can be driven from either port A or B.
The direction and output enable controls operate these devices
as either two independent 8-bit transceivers or one 16-bit trans-
ceiver.
LOGIC SYMBOL
OE1 (48)
OE2 (25)
(1)
DIR1
(47)
(46)
(44)
G1
G2
2EN1 (BA)
2EN2 (AB)
1EN1 (BA)
1EN2 (AB)
11
12
(24)
DIR2
1A1
1A2
1A3
(2)
(3)
(5)
(6)
(8)
1B1
1B2
1B3
1B4
(43)
1A4
(41)
1A5
(40)
1A6
(38)
1A7
(37)
1A8
(36)
2A1
2A2
2A3
(35)
(33)
21
22
1B5
(9)
1B6
(11)
1B7
(12)
1B8
(13)
2B1
(14)
2B2
(16)
2B3
(17)
2B4
(19)
2B5
(20)
2B6
(22)
2B7
(23)
2B8
(32)
2A4
(30)
2A5
(29)
2A6
(27)
2A7
(26)
2A8
1
PIN DESCRIPTION
Pin Names
OEx
DIRx
xAx
xBx
Description
Output Enable Input (Active Low)
Direction Control Inputs
Side A Inputs or 3-State Outputs (3.3V Port)
Side B Inputs or 3-State Outputs (5V Port)
PINOUTS
48-Lead Flatpack
Top View
DIR1
1B1
1B2
V
SS
1B3
OPERATION
B Data To A Bus
A Data To B Bus
Isolation
1B4
VDD1
1B5
1B6
V
SS
1B7
1B8
2B1
2B2
V
SS
2B3
2B4
VDD1
2B5
2B6
V
SS
2B7
2B8
DIR2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE1
1A1
1A2
V
SS
1A3
1A4
VDD2
1A5
1A6
V
SS
1A7
1A8
2A1
2A2
V
SS
2A3
2A4
VDD2
2A5
2A6
V
SS
2A7
2A8
OE2
FUNCTION TABLE
ENABLE
OEx
L
L
H
DIRECTION
DIRx
L
H
X
2
IO GUIDELINES
All inputs are 5 volt tolerant. When VDD2 is at 3.3 volts, either
3.3 or 5 volt CMOS logic levels can be applied to all control in-
puts. It is recommended that all unused inputs be tied to VSS
through a 1KΩ to 10KΩ resistor.
It's good design practice to tie the unused input to VSS via a re-
sistor to reduce noise susceptibility. The resistor protects the in-
put pin by limiting the current from high going variations in
VSS.
The number of inputs that can be tied to the resistor pull-down
can vary. It is up to the system designer to choose how many
inputs are tied together by figuring out the max load the part can
drivewhile still meeting system performance specs. Input signal
transitions should be driven to the device with a rise
and fall time that is <100ms.
POWER APPLICATION GUIDELINES
For proper operation, connect power to all V
DD
pins and ground
all V
SS
pins (i.e., no floating V
DD
or V
SS
input pins). By virtue
of the UT54ACS164245SEI warm spare feature, power supplies
V
DD1
and V
DD2
may be applied to the device in any order. To
ensure the device is in cold spare mode, both supplies, V
DD1
and
V
DD2
must be equal to V
SS
+/- 0.3V. Warm spare operation is
in effect when one power supply is >1V and the other power
supply is equal to V
SS
+/- 0.3V. If V
DD1
has a power on ramp
longer than 1 second, then V
DD2
should be powered on first to
ensure proper control of DIRx and OEx. During normal opera-
tion of the part, after power-up, ensure VDD1>VDD2.
By definition, warm sparing occurs when half of the chip re-
ceives its normal V
DD
supply value while the V
DD
supplying the
other half of the chip is set to 0.0V. When the chip is "warm
spared", the side that has V
DD
set to a normal operational value
is "actively" tri-stated because the chip’s internal OE signal is
forced low. The side of the chip that has V
DD
set to 0.0V is "pas-
sively" tri-stated by the cold spare circuitry. In order to mini-
mize transients and current consumption, the user is encouraged
to first apply a high level to the OEx pins and then power down
the appropriate supply.
POWER TABLE
Port B
5 Volts
5 Volts
3.3 Volts
V
SS
V
SS
3.3V or 5V
Port A
3.3 Volts
5 Volts
3.3 Volts
V
SS
3.3V or 5V
V
SS
OPERATION
Voltage Translator
Non Translating
Non Translating
Cold Spare
Port A Warm Spare
Port B Warm Spare
3
LOGIC DIAGRAM
DIR1
(1)
(48)
OE1
DIR2
(24)
(25)
OE2
1A1
(47)
(2)
1B1
2A1
(36)
(13)
2B1
1A2
(46)
(3)
1B2
2A2
(35)
(14)
2B2
1A3
(44)
(5)
1B3
2A3
(33)
(16)
2B3
3.3V PORT
3.3V PORT
1A4
(43)
2A4
(32)
(17)
2B4
5 V PORT
(6)
1A5
(41)
(8)
1A6
(40)
(9)
1A7
(38)
(11)
1A8
(37)
(12)
1B4
2A5
(30)
(19)
2B5
1B5
2A6
1B6
2A7
1B7
2A8
1B8
(26)
(27)
(29)
(20)
2B6
(22)
2B7
(23)
2B8
4
5 V PORT
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEL Immune
Neutron Fluence
2
LIMIT
1.0E5
>114
1.0E14
UNITS
rad(Si)
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
V
I/O
(Port B)
2
V
I/O
(Port A)
2
V
DD1
V
DD2
T
STG
T
J
Θ
JC
I
I
P
D
PARAMETER
Voltage any pin during operation
Voltage any pin during operation
Supply voltage
Supply voltage
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT (Mil only)
-.3 to V
DD1
+.3
-.3 to V
DD1
+.3
-0.3 to 6.0
-0.3 to 6.0
-65 to +150
+175
20
±10
1
UNITS
V
V
V
V
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
2. For cold spare mode (V
DD
= V
SS
), V
I/O
may be -0.3V to the maximum recommended operating V
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