HS-RTX2010RH
Data Sheet
March 2000
File Number
3961.3
Radiation Hardened Real Time Express™
Microcontroller
The HS-RTX2010RH is a radiation-hardened 16-bit
microcontroller with on-chip timers, an interrupt controller, a
multiply-accumulator, and a barrel shifter. It is particularly
well suited for space craft environments where very high
speed control tasks which require arithmetically intensive
calculations, including floating point math to be performed in
hostile space radiation environments.
This processor incorporates two 256-word stacks with
multitasking capabilities, including configurable stack
partitioning and over/underflow control.
Instruction execution times of one or two machine cycles are
achieved by utilizing a stack oriented, multiple bus
architecture. The high performance ASIC Bus, which is
unique to the RTX product, provides for extension of the
microcontroller architecture using off-chip hardware and
application specific I/O devices.
RTX Microcontrollers support the C and Forth programming
languages. The advantages of this product are further
enhanced through third party hardware and software support.
Combined, these features make the HS-RTX2010RH an
extremely powerful processor serving numerous
applications in high performance space systems. The
HS-RTX2010RH has been designed for harsh space
radiation environments and features outstanding Single
Event Upset (SEU) resistance and excellent total dose
response.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95635. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Features
• Electrically Screened to SMD # 5962-95635
• QML Qualified per MIL-PRF-38535 Requirements
• Fast 125ns Machine Cycle
• 1.2µM TSOS4 CMOS/SOS Process
• Total Dose Capability . . . . . . . . . . . . . . . . . . 300KRad(Si)
• Single Event Upset Critical LET . . . . . . . >120MeV/mg/cm
2
• Single Event Upset Error Rate . . . . <1 x 10
-10
Errors/Bit-Day
(Note)
• -55
o
C - 125
o
C, 5V
±10%
Operation
• Single Cycle Instruction Execution
• Fast Arithmetic Operations
- Single Cycle 16-Bit Multiply
- Single Cycle 16-Bit Multiply Accumulate
- Single Cycle 32-Bit Barrel Shift
- Hardware Floating Point Support
• C Software Development Environment
• Direct Execution of Fourth Language
• Single Cycle Subroutine Call/Return
• Four Cycle Interrupt Latency
• On-Chip Interrupt Controller
• Three On-Chip 16-Bit Timer/Counters
• Two On-Chip 256 Word Stacks
• ASIC Bus™ for Off-Chip Architecture Extension
• 1 Megabyte Total Address Space
• Word and Byte Memory Access
• Fully Static Design - DC to 8MHz Operation
• 84 Lead Quad Flat Package or 85 Pin Grid Array
• Third Party Software and Hardware Development Systems
NOTE: Single Event Upset error rates are Adams 10% worst case
environment under worst case conditions for upset.
Ordering Information
ORDERING NUMBER
5962F9563501QXC
5962F9563501QYC
5962F9563501V9A
5962F9563501VXC
5962F9563501VYC
INTERNAL
MKT. NUMBER
HS8-RTX2010RH-8
HS9-RTX2010RH-8
HS0-RTX2010RH-Q
HS8-RTX2010RH-Q
HS9-RTX2010RH-Q
TEMP. RANGE
(
o
C)
55 to 125
55 to 125
25
55 to 125
55 to 125
55 to 125
55 to 125
Applications
• Space Systems Embedded Control
• Digital Filtering
• Image Processing
• Scientific Instrumentation
• Optical Systems
• Control Systems
• Attitude/Orbital Control
HS8-RTX2010RH/Proto HS8-RTX2010RH/Proto
HS9-RTX2010RH/Proto HS9-RTX2010RH/Proto
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Copyright
©
Intersil Corporation 2000
Real Time Express™, RTX™, and ASIC Bus™ are trademarks of Intersil Corporation.
HS-RTX2010RH
PGA And CQFP
Pin/Signal Assignments
CQFP
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
PGA
PIN
L6
L8
K8
L9
L10
K9
L11
K10
J10
K11
J11
H10
H11
F10
G10
G11
G9
F9
F11
SIGNAL
NAME
MA11
MA12
MA13
VDD
MA14
MA15
MA16
MA17
MA18
MA19
GND
LDS
UDS
NEW
BOOT
PCLK
MR/W
MD00
MD01
(Continued)
TYPE
PGA And CQFP
Pin/Signal Assignments
CQFP
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
-
PGA
PIN
E11
E10
E9
D11
D10
C11
B11
C10
A11
B10
B9
A10
A9
B8
A8
B6
B7
A7
C7
C3
SIGNAL
NAME
MD02
MD03
MD04
GND
MD05
MD06
MD07
VDD
MD08
MD09
MD10
MD11
MD12
MD13
MD14
GND
MD15
GA00
GA01
-
(Continued)
TYPE
Output; Address Bus
Output; Address Bus
Output; Address Bus
Power
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Output; Address Bus
Ground
Output
Output
Output
Output
Output
Output
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
Ground
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
Power
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
I/O; Data Bus
Ground
I/O; Data Bus
Output; Address Bus
Output; Address Bus
Isolated Alignment Pin
Output Signal Descriptions
SIGNAL
OUTPUTS
NEW
BOOT
MR/W
UDS
LDS
GIO
GR/W
PCLK
TCLK
INTA
60
61
63
59
58
16
15
62
2
3
1
1
1
1
1
1
1
0
0
0
NEW: A HIGH on this pin indicates that an Instruction Fetch is in progress.
BOOT: A HIGH on this pin indicates that Boot Memory is being accessed. This pin can be set or reset by accessing
bit 3 of the Configuration Register.
MEMORY READ/WRITE: A LOW on this pin indicates that a Memory Write operation is in progress.
UPPER DATA SELECT: A HIGH on this pin indicates that the high byte of memory (MD15-MD08) is being
accessed.
LOWER DATA SELECT: A HIGH on this pin indicates that the low byte of memory (MD07-MD00) is being
accessed.
ASIC I/O: A LOW on this pin indicates that an ASIC Bus operation is in progress.
ASIC READ/WRITE: A LOW on this pin indicates that an ASIC Bus Write operation is in progress.
PROCESSOR CLOCK: Runs at half the frequency of ICLK. All processor cycles begin on the rising edge of PCLK.
Held low extra cycles when WAIT is asserted.
TIMING CLOCK: Same frequency and phase as PCLK but continues running during Wait cycles.
INTERRUPT ACKNOWLEDGE: A HIGH on this pin indicates that an Interrupt Acknowledge cycle is in progress.
CQFP
RESET
LEVEL
DESCRIPTION
Input Signal, Bus, and Power Connection Descriptions
SIGNAL
INPUTS
WAIT
ICLK
RESET
13
14
12
WAIT: A HIGH on this pin causes PCLK to be held LOW and the current cycle to be extended.
INPUT CLOCK: Internally divided by 2 to generate all on-chip timing (CMOS input levels).
A HIGH level on this pin resets the RTX. Must be held high for at least 4 rising edges of ICLK plus 12 ICLK cycle
setup and hold times.
CQFP
LEAD
DESCRIPTION
4
HS-RTX2010RH
Input Signal, Bus, and Power Connection Descriptions
SIGNAL
EI2, EI1
EI5-EI3
CQFP
LEAD
8, 7
11-9
(Continued)
DESCRIPTION
EXTERNAL INTERRUPTS 2, 1: Active HIGH level-sensitive inputs to the Interrupt Controller. Sampled on the rising
edge of PCLK. See Timing Diagrams for detail.
EXTERNAL INTERRUPTS 5, 4, 3: Dual purpose inputs; active HIGH level-sensitive Interrupt Controller inputs;
active HIGH edge-sensitive Timer/Counter inputs. As interrupt inputs, they are sampled on the rising edge of PCLK.
See Timing Diagrams for detail.
NON-MASKABLE INTERRUPT: Active HIGH edge-sensitive Interrupt Controller input capable of interrupting any
processor cycle when NMI is set to Mode 0. See the Interrupt Suppression and Interrupt Controller Sections.
INTERRUPT SUPPRESS: A HIGH on this pin inhibits all maskable interrupts, internal and external.
NMI
INTSUP
4
5
ADDRESS BUSES (OUTPUTS)
GA02
GA01
GA00
MA19-MA14
MA13-MA09
MA08-MA01
DATA BUSES (I/O)
GD15-GD13
GD12-GD07
GD06-GD03
GD02-GD00
MD15
MD14-MD08
MD07-MD05
MD04-MD00
17-19
21-26
28-31
33-35
82
80-74
72-70
68-64
MEMORY DATA: 16-bit bidirectional Memory Data Bus, which carries data to and from Main Memory.
ASIC DATA: 16-bit bidirectional external ASIC Data Bus, which carries data to and from off-chip I/O devices.
1
84
83
56-51
49-45
43-36
MEMORY ADDRESS: 19-bit Memory Address Bus, which carries address information for Main Memory.
ASIC ADDRESS: 3-bit ASIC Address Bus, which carries address information for external ASIC devices.
POWER CONNECTIONS
VDD
GND
6, 27,
50, 73
20, 32,
44, 57,
69, 81
Power supply +5V connections. A 0.1µF, low impedance decoupling capacitor should be placed between VDD and
GND. This should be located as close to the RTX package as possible.
Power supply ground return connections.
TYPICAL
CLOCK OR
STROBE
t
PULSE WIDTH
4.0V
0.5V
t
SETUP
2.25V
t
PULSE WIDTH
2.25V
t
HOLD
2.25V
TYPICAL
INPUT
4.0V
0.5V
t
DELAY
2.25V
2.25V
t
DELAY
TYPICAL
OUTPUT
t
VALID
TYPICAL
DATA
OUTPUT
2.25V
t
HOLD
2.25V
2.75V
1.75V
2.75V
1.75V
FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT
5
FPGA/CPLD
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