MT46H32M32LFMA-6AT:B datasheet, PDF

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MT46H32M32LFMA-6AT:B: DescriptionDDR DRAM, 32MX32, 5ns, CMOS, PBGA168, 12 X 12 MM, GREEN, PLASTIC, WFBGA-168; Categorystorage storage; File Size1MB，100 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT46H32M32LFMA-6AT:B Overview

DDR DRAM, 32MX32, 5ns, CMOS, PBGA168, 12 X 12 MM, GREEN, PLASTIC, WFBGA-168

MT46H32M32LFMA-6AT:B Parametric

Parameter Name	Attribute value
Maker	Micron Technology
Parts packaging code	BGA
package instruction	VFBGA,
Contacts	168
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	S-PBGA-B168
JESD-609 code	e1
length	14 mm
memory density	1073741824 bit
Memory IC Type	DDR DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	168
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
organize	32MX32
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	SQUARE
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Maximum seat height	0.8 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
width	14 mm
Base Number Matches	1

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1Gb: x16, x32 Mobile LPDDR SDRAM

Features

Mobile Low-Power DDR SDRAM

MT46H64M16LF – 16 Meg x 16 x 4 banks

MT46H32M32LF – 8 Meg x 32 x 4 banks

Features

• V

DDQ

= 1.70–1.95V

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• 4 internal banks for concurrent operation

• Data masks (DM) for masking write data; one mask

per byte

• Programmable burst lengths (BL): 2, 4, 8, or 16

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS-compatible inputs

• Temperature-compensated self refresh (TCSR)

• Partial-array self refresh (PASR)

• Deep power-down (DPD)

• Status read register (SRR)

• Selectable output drive strength (DS)

• Clock stop capability

• 64ms refresh, 32ms for automotive temperature

Table 1: Key Timing Parameters (CL = 3)

Speed Grade

-5

-54

-6

-75

Clock Rate

200 MHz

185 MHz

166 MHz

133 MHz

Access Time

5.0ns

6.0ns

Options

• V

DDQ

– 1.8V/1.8V

• Configuration

– 64 Meg x 16 (16 Meg x 16 x 4

banks)

– 32 Meg x 32 (8 Meg x 32 x 4 banks)

• Addressing

– JEDEC-standard

• Plastic "green" package

– 60-ball VFBGA (8mm x 9mm)

– 90-ball VFBGA (8mm x 13mm)

• PoP (plastic "green" package)

– 168-ball WFBGA (12mm x 12mm)

• Timing – cycle time

– 5ns @ CL = 3 (200 MHz)

– 5.4ns @ CL = 3 (185 MHz)

– 6ns @ CL = 3 (166 MHz)

– 7.5ns @ CL = 3 (133 MHz)

• Power

– Standard I

DD2

DD6

• Operating temperature range

– Commercial (0˚ to +70˚C)

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

• Design revision

Notes:

Marking

64M16

32M32

-5

-54

-6

-75

None

1. Only available for x16 configuration.

2. Only available for x32 configuration.

3. Contact factory for availability.

PDF: 09005aef83d9bee4

1gb_ddr_mobile_sdram_t68m.pdf - Rev. J 1/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

1Gb: x16, x32 Mobile LPDDR SDRAM

Features

Contents

General Description ......................................................................................................................................... 8

Functional Block Diagrams ............................................................................................................................... 9

Ball Assignments and Descriptions ................................................................................................................. 11

Package Dimensions ....................................................................................................................................... 16

Electrical Specifications .................................................................................................................................. 19

Electrical Specifications – I

Parameters ........................................................................................................ 23

Electrical Specifications – AC Operating Conditions ......................................................................................... 29

Output Drive Characteristics ........................................................................................................................... 34

Functional Description ................................................................................................................................... 37

Commands .................................................................................................................................................... 38

DESELECT ................................................................................................................................................. 39

NO OPERATION ......................................................................................................................................... 39

LOAD MODE REGISTER ............................................................................................................................. 39

ACTIVE ...................................................................................................................................................... 39

READ ......................................................................................................................................................... 40

WRITE ....................................................................................................................................................... 41

PRECHARGE .............................................................................................................................................. 42

BURST TERMINATE ................................................................................................................................... 43

AUTO REFRESH ......................................................................................................................................... 43

SELF REFRESH ........................................................................................................................................... 44

DEEP POWER-DOWN ................................................................................................................................. 44

Truth Tables ................................................................................................................................................... 45

State Diagram ................................................................................................................................................ 50

Initialization .................................................................................................................................................. 51

Standard Mode Register .................................................................................................................................. 54

Burst Length .............................................................................................................................................. 55

Burst Type .................................................................................................................................................. 55

CAS Latency ............................................................................................................................................... 56

Operating Mode ......................................................................................................................................... 57

Extended Mode Register ................................................................................................................................. 58

Temperature-Compensated Self Refresh ...................................................................................................... 58

Partial-Array Self Refresh ............................................................................................................................ 59

Output Drive Strength ................................................................................................................................ 59

Status Read Register ....................................................................................................................................... 60

Bank/Row Activation ...................................................................................................................................... 62

READ Operation ............................................................................................................................................. 63

WRITE Operation ........................................................................................................................................... 74

PRECHARGE Operation .................................................................................................................................. 86

Auto Precharge ............................................................................................................................................... 86

Concurrent Auto Precharge ......................................................................................................................... 87

AUTO REFRESH Operation ............................................................................................................................. 92

SELF REFRESH Operation ............................................................................................................................... 93

Power-Down .................................................................................................................................................. 94

Deep Power-Down ..................................................................................................................................... 96

Clock Change Frequency ................................................................................................................................ 98

Revision History ............................................................................................................................................. 99

Rev. J – 1/14 ................................................................................................................................................ 99

Rev. I – 10/13 .............................................................................................................................................. 99

Rev. H – 6/13 .............................................................................................................................................. 99

Rev. G – 9/11 .............................................................................................................................................. 99

PDF: 09005aef83d9bee4

1gb_ddr_mobile_sdram_t68m.pdf - Rev. J 1/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

1Gb: x16, x32 Mobile LPDDR SDRAM

Features

List of Figures

Figure 1: 1Gb Mobile LPDDR Part Numbering .................................................................................................. 2

Figure 2: Functional Block Diagram (x16) ......................................................................................................... 9

Figure 3: Functional Block Diagram (x32) ....................................................................................................... 10

Figure 4: 60-Ball VFBGA – Top View, x16 only .................................................................................................. 11

Figure 5: 90-Ball VFBGA – Top View, x32 only .................................................................................................. 12

Figure 6: 168-Ball FBGA – 12mm x 12mm (Top View), x32 only ........................................................................ 13

Figure 7: 60-Ball VFBGA (8mm x 9mm), Package Code: BF .............................................................................. 16

Figure 8: 90-Ball VFBGA (8mm x 13mm), Package Code: B5 ............................................................................. 17

Figure 9: 168-Ball WFBGA (12mm x 12mm), Package Code: MA ....................................................................... 18

Figure 10: Typical Self Refresh Current vs. Temperature .................................................................................. 28

Figure 11: ACTIVE Command ........................................................................................................................ 40

Figure 12: READ Command ........................................................................................................................... 41

Figure 13: WRITE Command ......................................................................................................................... 42

Figure 14: PRECHARGE Command ................................................................................................................ 43

Figure 15: DEEP POWER-DOWN Command ................................................................................................... 44

Figure 16: Simplified State Diagram ............................................................................................................... 50

Figure 17: Initialize and Load Mode Registers ................................................................................................. 52

Figure 18: Alternate Initialization with CKE LOW ............................................................................................ 53

Figure 19: Standard Mode Register Definition ................................................................................................. 54

Figure 20: CAS Latency .................................................................................................................................. 57

Figure 21: Extended Mode Register ................................................................................................................ 58

Figure 22: Status Read Register Timing ........................................................................................................... 60

Figure 23: Status Register Definition .............................................................................................................. 61

Figure 24: READ Burst ................................................................................................................................... 64

Figure 25: Consecutive READ Bursts .............................................................................................................. 65

Figure 26: Nonconsecutive READ Bursts ........................................................................................................ 66

Figure 27: Random Read Accesses .................................................................................................................. 67

Figure 28: Terminating a READ Burst ............................................................................................................. 68

Figure 29: READ-to-WRITE ............................................................................................................................ 69

Figure 30: READ-to-PRECHARGE .................................................................................................................. 70

Figure 31: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x16) .................................................... 71

Figure 32: Data Output Timing –

DQSQ,

QH, and Data Valid Window (x32) .................................................... 72

Figure 33: Data Output Timing –

AC and

DQSCK .......................................................................................... 73

Figure 34: Data Input Timing ......................................................................................................................... 75

Figure 35: Write – DM Operation .................................................................................................................... 76

Figure 36: WRITE Burst ................................................................................................................................. 77

Figure 37: Consecutive WRITE-to-WRITE ....................................................................................................... 78

Figure 38: Nonconsecutive WRITE-to-WRITE ................................................................................................. 78

Figure 39: Random WRITE Cycles .................................................................................................................. 79

Figure 40: WRITE-to-READ – Uninterrupting ................................................................................................. 80

Figure 41: WRITE-to-READ – Interrupting ...................................................................................................... 81

Figure 42: WRITE-to-READ – Odd Number of Data, Interrupting ..................................................................... 82

Figure 43: WRITE-to-PRECHARGE – Uninterrupting ....................................................................................... 83

Figure 44: WRITE-to-PRECHARGE – Interrupting ........................................................................................... 84

Figure 45: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting .......................................................... 85

Figure 46: Bank Read – With Auto Precharge ................................................................................................... 88

Figure 47: Bank Read – Without Auto Precharge .............................................................................................. 89

Figure 48: Bank Write – With Auto Precharge .................................................................................................. 90

Figure 49: Bank Write – Without Auto Precharge ............................................................................................. 91

Figure 50: Auto Refresh Mode ........................................................................................................................ 92

PDF: 09005aef83d9bee4

1gb_ddr_mobile_sdram_t68m.pdf - Rev. J 1/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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