SI5341B-D07445-GMR datasheet, PDF

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SI5341B-D07445-GMR: DescriptionProcessor Specific Clock Generator,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size5MB，53 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

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SI5341B-D07445-GMR Overview

Processor Specific Clock Generator,

SI5341B-D07445-GMR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	HVQCCN,
Reach Compliance Code	unknow
JESD-30 code	S-XQCC-N64
length	9 mm
Humidity sensitivity level	2
Number of terminals	64
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	350 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	750 MHz
Maximum seat height	0.9 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	9 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches	1

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Si5341/40 Rev D Data Sheet

Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock

Generator

The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL

with proprietary MultiSynth

™

fractional synthesizer technology to offer a versatile and

high performance clock generator platform. This highly flexible architecture is capable

of synthesizing a wide range of integer and non-integer related frequencies up to 1

GHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter per-

formance with 0 ppm error. Each of the clock outputs can be assigned its own format

and output voltage enabling the Si5341/40 to replace multiple clock ICs and oscillators

with a single device making it a true "clock tree on a chip."

The Si5341/40 can be quickly and easily configured using ClockBuilderPro software.

Custom part numbers are automatically assigned using a

ClockBuilder Pro

™

for fast,

free, and easy factory pre-programming or the Si5341/40 can be programmed via I2C

and SPI serial interfaces.

KEY FEATURES

• Generates any combination of output

frequencies from any input frequency

• Ultra-low jitter of 90 fs rms

• Input frequency range:

• External crystal: 25 to 54 MHz

• Differential clock: 10 to 750 MHz

• LVCMOS clock: 10 to 250 MHz

• Output frequency range:

• Differential: 100 Hz to 1028 MHz

• LVCMOS: 100 Hz to 250 MHz

• Highly configurable outputs compatible with

LVDS, LVPECL, LVCMOS, CML, and HCSL

with programmable signal amplitude

• Si5341: 4 input, 10 output, 64-QFN 9x9 mm

• Si5340: 4 input, 4 output, 44-QFN 7x7 mm

Applications:

• Clock tree generation replacing XOs, buffers, signal format translators

• Any-frequency clock translation

• Clocking for FPGAs, processors, memory

• Ethernet switches/routers

• OTN framers/mappers/processors

• Test equipment and instrumentation

• Broadcast video

25-54 MHz XTAL

4 Input

Clocks

IN0

IN1

IN2

OSC

÷INT

PLL

MultiSynth

÷INT

Zero Delay

OUT0

OUT1

Si5340

Up to 10

Output Clocks

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

Si5341

OUT8

OUT9

FB_IN

Status Flags

I2C / SPI

÷INT

Status Monitor

Control

NVM

÷INT

silabs.com

| Smart. Connected. Energy-friendly.

Rev. 1.0

Si5341/40 Rev D Data Sheet

Functional Description

3. Functional Description

The Si5340/41-D combines a wide band PLL with next generation MultiSynth technology to offer the industry's most versatile and high

performance clock generator. The PLL locks to either an external

crystal

between XA/XB or to an external

clock

connected to XA/XB

or IN0, 1, 2. A fractional or integer multiplier takes the selected input clock or cystal frequency up to a very high frequency that is then

divided by the MultiSynth output stage to any frequency in the range of 100 Hz to 1 GHz on each output. The MultiSynth stage can

divide by both integer and fractional values. The high-resolution fractional MultiSynth dividers enable true any-frequency input to any-

frequency on any of the outputs. The output drivers offer flexible output formats which are independently configurable on each of the

outputs. This clock generator is fully configurable via its serial interface (I

C/SPI) and includes in-circuit programmable non-volatile

memory.

3.1 Power-up and Initialization

Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from

NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-

tion period is complete. No clocks will be generated until the initialization is done. There are two types of resets available. A hard reset

is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be restored to

their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard reset bit. A soft reset

bypasses the NVM download. It is simply used to initiate register configuration changes.

Power-Up

Hard Reset

bit asserted

RSTb

pin asserted

NVM download

Soft Reset

bit asserted

Initialization

Serial interface

ready

Figure 3.1. Si5341 Power-Up and Initialization

3.2 Frequency Configuration

The phase-locked loop is fully contained and does not require external loop filter components to operate. Its function is to phase lock to

the selected input and provide a common reference to the MultiSynth high-performance fractional dividers.

A crosspoint mux connects any of the MultiSynth divided frequencies to any of the outputs drivers. Additional output integer dividers

provide further frequency division by an even integer from 2 to (2^25)-2. The frequency configuration of the device is programmed by

setting the input dividers (P), the PLL feedback fractional divider (Mn/Md), the MultiSynth fractional dividers (Nn/Nd), and the output

integer dividers (R). Silicon Labs's ClockBuilder Pro configuration utility determines the optimum divider values for any desired input

and output frequency plan.

3.3 Inputs

The Si5340/41-D requires either an external crystal at its XA/XB pins or an external clock at XA/XB or IN0, 1, 2.

silabs.com

| Smart. Connected. Energy-friendly.

Rev. 1.0 | 4

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