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5962R9652801VCX

Description
NOR Gate, AC Series, 3-Func, 3-Input, CMOS, CDIP14, CERAMIC, SIDE BRAZED, DIP-14
Categorylogic    logic   
File Size224KB,9 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

5962R9652801VCX Overview

NOR Gate, AC Series, 3-Func, 3-Input, CMOS, CDIP14, CERAMIC, SIDE BRAZED, DIP-14

5962R9652801VCX Parametric

Parameter NameAttribute value
MakerCobham Semiconductor Solutions
Parts packaging codeDIP
package instructionDIP,
Contacts14
Reach Compliance Codeunknown
seriesAC
JESD-30 codeR-CDIP-T14
length19.43 mm
Logic integrated circuit typeNOR GATE
Number of functions3
Number of entries3
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)15 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
total dose100k Rad(Si) V
width7.62 mm
Base Number Matches1
Standard Products
UT54ACS27/UT54ACTS27
Triple 3-Input NOR Gates
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ
CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS27 - SMD 5962-96528
UT54ACTS27 - SMD 5962-96529
DESCRIPTION
The UT54ACS27 and the UT54ACTS27 are triple, three-input
NOR gates. The circuits perform the Boolean functions
Y = A+B+C or Y = A⋅B⋅C in positive logic.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUTS
A
H
X
X
L
B
X
H
X
L
C
X
X
H
L
OUTPUT
Y
L
L
L
H
PINOUTS
14-Pin DIP
Top View
A1
B1
A2
B2
C2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
C1
Y1
C3
B3
A3
Y3
14-Lead Flatpack
Top View
A1
B1
A2
B2
C2
Y2
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
C1
Y1
C3
B3
A3
Y3
LOGIC DIAGRAM
LOGIC SYMBOL
A1
B1
C1
A2
B2
C2
A3
B3
C3
(1)
(2)
(13)
(3)
(4)
(5)
(9)
(10)
(11)
(8)
Y3
(6)
Y2
≥1
(12)
A1
B1
C1
A2
B2
C2
A3
B3
C3
Y1
Y1
Y2
Y3
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
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