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595DC525M000DG

Description
Oscillator
CategoryPassive components    oscillator   
File Size89KB,12 Pages
ManufacturerSilicon Laboratories Inc
Download Datasheet Parametric View All

595DC525M000DG Overview

Oscillator

595DC525M000DG Parametric

Parameter NameAttribute value
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Base Number Matches1
Si595
R
EVISION
D
V
O L TAG E
- C
ONTR OLLED
C
RYSTAL
O
S C I L L A T O R
(VCXO)
10
TO
525 MH
Z
Features
Available with any-rate output
frequencies from 10 to 525 MHz
3rd generation DSPLL
®
with
superior jitter performance
Internal fixed fundamental mode
crystal frequency ensures high
reliability and low aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
–40 to +85 ºC operating range
Si5602
Applications
Ordering Information:
SONET/SDH (OC-3/12/48)
Networking
SD/HD SDI/3G SDI video
FTTx
Clock recovery and jitter cleanup PLLs
FPGA/ASIC clock generation
See page 7.
Description
The Si595 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to
provide a low-jitter clock at high frequencies. The Si595 is available with
any-rate output frequency from 10 to 525 MHz. Unlike traditional VCXOs,
where a different crystal is required for each output frequency, the Si595
uses one fixed crystal to provide a wide range of output frequencies. This IC-
based approach allows the crystal resonator to provide exceptional
frequency stability and reliability. In addition, DSPLL clock synthesis
provides supply noise rejection, simplifying the task of generating low-jitter
clocks in noisy environments. The Si595 IC-based VCXO is factory-
configurable for a wide variety of user specifications including frequency,
supply voltage, output format, tuning slope, and absolute pull range (APR).
Specific configurations are factory programmed at time of shipment, thereby
eliminating the long lead times associated with custom oscillators.
Pin Assignments:
See page 6.
(Top View)
V
C
1
6
V
DD
OE
2
5
CLK–
GND
3
4
CLK+
Functional Block Diagram
V
DD
CLK–
CLK+
Fixed
Frequency
XO
Any-rate
10–525 MHz
DSPLL
®
Clock Synthesis
ADC
Vc
OE
GND
Preliminary Rev. 0.2 8/09
Copyright © 2009 by Silicon Laboratories
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